rx_path_top (LiteX)

Description

Top module for packaging IQ samples received from the RF transceiver into stream packets.

Functionality:

• Pack IQ samples from the stream sink into packets and write them into a FIFO buffer.

• Pack 12-bit IQ samples into 128-bit words to efficiently use data-transfer bandwidth.

• Store stream packets in an AXI-Stream (AXIS) buffer.

Main block diagram

The top-level file integrates the following main blocks:

• Channel combiner (chnl_combiner) – Selects the channels for data collection and combines them into 128-bit words.

• Bit Width Selector (BitWidthSelector) – Selects bit width for IQ samples

• Packet forming state machine (Data2packetsFSM) – Packet formation logic

• Sample Synchronization Counter (smpl_cnt0) – Sample synchronization counter for TX path

• Source Endpoint Conversion (ep_conv) – Converts source endpoint from internal 128-bit width to the desired source width

• Source Endpoint CDC (source_ep_cdc) – Source Endpoint clock domain crossing

This diagram represents the top-level Receive (RX) path. Its primary function is to ingest streaming data (IQ samples), adjust its bit-width, format it into packets, and transfer it safely from the input clock domain to the system’s main clock domain.

Clock domains

This module operates in two clock domains:

• Sink clock domain — The left side of the diagram operates in the sink clock domain.

• Source clock domain — The far-right output operates on a different clock (source clock).

Channel Combiner

This block interfaces with the sink bus where multiple IQ channels are interleaved. It filters for a specific, user-configured channel and consolidates those samples into 128-bit-wide words.

Example Scenario: If the RX path receives four channels spaced across the 128-bit input bus, but the module is configured to capture only Channel A:

1. The block isolates samples belonging to Channel A.

2. It discards data from the other three channels.

3. It accumulates the Channel A samples until they fill a 128-bit word.

4. The output is a 128-bit stream containing only interleaved Channel A data.

Bit Width Selector

This module packs 12-bit samples into 128-bit words, or—if samples are 16-bit—passes them through to 128-bit words. This block has two data paths, which are selected with a multiplexer and demultiplexer:

1. Gearbox Path: Used when IQ samples are 12-bit wide. The ep_gearbox module takes 96 bits from the sink bus and packs them into a 128-bit bus.

2. Bypass Path: Used when IQ samples are 16-bit wide. The sink bus is directly connected to the source.

A First-In-First-Out buffer, source_fifo, located at the output of this block is used to handle back-pressure.

Packet forming state machine

This block transforms a continuous stream of IQ data into packets. Packets consist of a 64-bit header, a 64-bit sample counter, and a payload of configurable size. It uses the following internal modules:

• data2packets_fsm: A finite state machine that controls the packet generation flow. It manages packet-forming logic and controls the writing of data into the FIFO.

• smpl_cnt1: The sample counter tracks the number of IQ samples processed. It is used to generate sequence numbers/timestamps for packet headers.

• source_fifo: A secondary buffering stage that stores the organized packet data and handles back-pressure.

Field	Byte Offset	Size	Description
Header	0 - 7	8 Bytes	General packet header.
Counter	8 - 15	8 Bytes	Sample counter (increased for each IQ sample frame).
Payload	16 - 4095	4080 Bytes	Payload structure depends on the channels enabled: Channel A enabled: [AI0, AQ0, AI1, AQ1, … , AIn, AQn] Channels A and B enabled: [AI0, AQ0, BI0, BQ0, … , AIn, AQn, BIn, BQn] Channels A, B, C, and D enabled: [AI0, AQ0, BI0, BQ0, CI0, CQ0, DI0, DQ0, … , AIn, AQn, BIn, BQn, CIn, CQn, DIn, DQn]

Sample Synchronization Counter

This 64-bit counter is used for TX sample synchronization. It counts incoming samples, incrementing on a valid/ready handshake on the sink stream bus.

Source Endpoint Conversion

In cases where downstream modules expect a wider/narrower bus width, the ep_conv module converts the source endpoint from an internal 128-bit width to the desired source width. It is up to the user to calculate the proper bus width and use a fast-enough clock source to handle the desired bandwidth.

Source Endpoint CDC

In cases where downstream modules expect a different clock domain, the asynchronous FIFO source_ep_cdc module is used to ensure proper clock-domain crossing.

Timing diagram

This timing diagram can be used as a reference to get familiar with module behavior.