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Lime Digital Function Blocks
General
Introduction
Contributing
HDL Coding Guidelines
Introduction
1. Layout
2. Naming Conventions
3. Packages and libraries
3. Annexes
Annex 1: VHDL module template
Annex 2: VHDL testbench template
Annex 3: Configuration file for VHDL VSG
Creating LiteX wrappers
Introduction
1. Prerequisites
1.1 What a LiteX Wrapper Should Contain
2. Adding Litex CSRs
3. Internal signals
4. HDL module instance
5. Include HDL sources
5. Complete example
DFB List
Available modules
lms7002_top
Description
Main block diagram:
rx_path_top
Description
Main block diagram:
rx_path_top (LiteX)
Description
Main block diagram
Clock domains
Channel Combiner
Bit Width Selector
Packet forming state machine
Sample Synchronization Counter
Source Endpoint Conversion
Source Endpoint CDC
Timing diagram
tx_path_top
Description
Main block diagram:
tx_path_top (LiteX)
Description
Main block diagram
Clock domains
Packet format (expected at sink)
Input CDC (input_buff)
Slave Width Converter (conv_64_to_128)
Packet Buffer Write (PCT2DATA_BUF_WR)
Per-Packet AXIS FIFOs (axis_fifo)
Packet Buffer Read (PCT2DATA_BUF_RD)
Sample Padder (sample_padder)
Sample Unpack (SAMPLE_UNPACK / sample_unpack128)
Sample Nr CDC (smpl_nr_fifo)
Interfaces and control
Key parameters
Notes
Timing diagram
afe79xx
Functionality
Main Block Diagram
AFE79xx JESD IP Core
TX/RX CDC
TX/RX Converters
Interleaver/Deinterleaver
TX/RX Channel Multiplexer
Resamplers
Lime Digital Function Blocks
Index
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Index