Gateware Overview

This page is a quick entry point to LimeSDR gateware documentation. Use it to navigate architecture, host interfaces, toolchains, and update workflow topics, then follow the linked pages for full detail.

Recommended Reading Order

1. Gateware Architecture: top-level subsystem layout (HIF/CPU/LimeTOP/PSS), control vs data plane, and interconnect model.

   Board-specific architecture/implementation pages:

   • LimeSDR XTRX

   • LimeSDR Mini V1

   • LimeSDR Mini V2

   • HiperSDR 44xx

   • sSDR rev2

2. Gateware Toolchains and Firmware Toolchains: required build environments for FPGA synthesis and CPU firmware compilation.

3. Update and Recovery: flash update flow, multiboot behavior, and practical recovery/verification steps.

Additional Features

Some LimeSDR boards offer auxiliary features. See Additional features.