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LimeSDR FPGA Gateware
  • Introduction
  • Quick Start
    • Requirements
    • Cloning the Repository
    • Build, Load, and Flash
      • LimeSDR XTRX
        • Available Build Options
        • User and Golden Bitstreams
        • Programming Hardware
          • FT2232H Mini Module Connection
        • Flashing Instructions
      • LimeSDR Mini V1
        • Available Build Options
        • User and Golden Bitstreams
        • Programming Cables
        • Flashing Instructions
      • LimeSDR Mini V2
        • Available Build Options
        • User and Golden Bitstreams
        • Programming Cables
        • Flashing Instructions
      • HiperSDR-44xx
        • Available Build Options
        • User and Golden Bitstreams
        • Programming Cables
          • JTAG Programming (openFPGALoader)
          • FT2232H Mini Module JTAG Adapter
        • Flashing Instructions
      • sSDR rev2
        • Available Build Options
        • User and Golden Bitstreams
        • Programming Cables
          • FT2232H Mini Module JTAG Adapter
          • Digilent HS2 JTAG Adapter
        • Flashing Instructions
  • Project Structure
    • At a Glance
    • LimeSDR_GW Repository
      • Repository layout
      • Important directories
      • Typical role in the build flow
    • LimeDFB Repository
      • Repository layout
      • Important directories
      • Typical role in the build flow
    • How the Repositories Work Together
    • Other Important Files
    • See Also
  • Gateware Overview
    • Recommended Reading Order
      • Gateware Architecture
        • Architectural Domains
          • HIF - Host Interface Subsystem
          • CPU - Embedded Control Subsystem
          • LimeTOP - RF Processing Subsystem
          • PSS - Peripheral Support Subsystem
        • Interconnect
        • External Interfaces
        • Board Implementations
      • Gateware Toolchains
        • FPGA Synthesis Toolchains
      • Firmware Toolchains
        • RISC-V Firmware Toolchains
        • Installation
      • Update and Recovery
        • Overview
        • Update Process
        • Multiboot Across FPGAs
        • Testing and Recovery
      • LimeSDR XTRX
        • Main Block Diagram
          • Soft core CPU Module
          • Lime_top Module
          • LMS7002 Top Module
          • RX Path Top Module
          • TX Path Top Module
          • PCIe PHY Module
          • I2C Modules
          • LMS SPI Module
        • Flash Module
        • Gateware Register Reference
          • Legacy FPGA SPI register reference
          • Documentation for limesdr-xtrx
          • Modules
          • Register Groups
          • Indices and tables
      • LimeSDR Mini V1
        • Main Block Diagram
        • Soft core CPU Module
        • Lime_top Module
          • LMS7002 Top Module
          • RX Path Top Module
          • TX Path Top Module
        • FT601 PHY Module
        • I2C Module
        • Lms_spi Module
        • Flash Module
        • Gateware Register Reference
          • Legacy FPGA SPI register reference
          • Documentation for limesdr-mini-v1
          • Modules
          • Register Groups
          • Indices and tables
      • LimeSDR Mini V2
        • Main Block Diagram
        • Soft core CPU Module
        • Lime_top Module
          • LMS7002 Top Module
          • RX Path Top Module
          • TX Path Top Module
        • FT601 PHY Module
        • I2C Module
        • Lms_spi Module
        • Flash Module
        • Gateware Register Reference
          • Legacy FPGA SPI register reference
          • Documentation for limesdr-mini-v2
          • Modules
          • Register Groups
          • Indices and tables
      • HiperSDR 44xx
        • Main Block Diagram
          • Soft core CPU Module
          • AFE79xx
          • LimeTop Module
          • RX Path Top Module
          • TX Path Top Module
          • PCIe PHY Module
          • I2C Modules
          • SPI Modules
          • Flash Module
        • HiperSDR_44xx RF controls
        • Gateware Register Reference
          • Legacy FPGA SPI register reference
          • Documentation for hipersdr-44xx
          • Modules
          • Register Groups
          • Indices and tables
      • sSDR rev2
        • Main Block Diagram
          • Soft core CPU Module
          • Lime_top Module
          • LMS7002 Top Module
          • RX Path Top Module
          • TX Path Top Module
          • PCIe PHY Module
          • I2C Modules
          • SPI Module
        • Flash Module
        • Gateware Register Reference
          • Legacy FPGA SPI register reference
          • Documentation for ssdr_rev2
          • Modules
          • Register Groups
          • Indices and tables
      • Additional features
        • Compatibility table
          • UTC timestamping
    • Additional Features
  • LiteX Basics
    • Introduction to LiteX in LimeSDR_GW
      • Overview of LiteX usage in LimeSDR_GW
      • Benefits of Using LiteX (in the Context of LimeSDR_GW)
    • Understanding Core LiteX Concepts: Boards, Platforms, Targets
      • Platform = Board + Constraints
      • LMS7002M I/O Block on LimeSDR Mini V2
      • Timing Constraints Generation
      • Multiple Toolchain Support
      • Target = SoC Top-Level + Flow Control
      • How It All Fits Together
    • Creating LiteX/Migen Wrappers
      • Example: Wrapping the GPIO Module
      • General Pattern
  • Modifying the Project
    • Gateware
      • FFT module example
        • Instantiating FFT Example module
        • Connecting FFT Example module
        • Checking FFT results
    • Firmware
    • Firmware Loading via UART
    • Debug Tools
  • Adding a New Board
    • Tutorial: Developing New LimeDFB Blocks
    • Tutorial: Adding a Custom Board
  • Best Practices and Guidelines
    • Introduction
    • File, Module, and Signal Naming Conventions
      • Module and File Structure
      • Class Naming
      • Signal Naming
      • AXIStream Interfaces
      • CSRs and Registers
      • Platform Naming and IO Mapping
      • Recommendations
    • Developing for Portability Across Devices and Vendors
      • Unified Platform and IO Abstraction
      • Cross-Vendor IO Support: Abstracted Primitives
      • Cross-Vendor PLL and Clocking
      • Memory Abstraction and Flexibility
      • Simplified Toolchain Integration
      • Avoiding Fragmentation of CPU and Firmware
    • Soft CPU Core Options
      • Supported CPUs in LiteX
      • Tested Cores in LimeSDR_GW
      • Typical Firmware Workloads
      • Unified Firmware and Tooling
LimeSDR FPGA Gateware
  • Gateware Overview
  • LimeSDR XTRX
  • Documentation for limesdr-xtrx
  • Edit on GitHub

Documentation for limesdr-xtrx

Modules

  • Interrupt Controller

Register Groups

  • UART
  • ICAP
  • PCIE_PHY
  • PCIE_MSI
  • AUX
  • PCIE_DMA0
  • CTRL
  • GPIO
  • IDENTIFIER_MEM
  • LEDS
  • LIME_TOP
  • LMS_CLOCK_TEST
  • MAIN
  • PCIE_UART0
  • PCIE_UART1
  • FLASH
  • XADC
  • DNA
  • I2C0
  • I2C1
  • PCIE_ENDPOINT
  • PERIPHCFG
  • PPSDO
  • SPIMASTER
  • SYS_CLOCK_TEST
  • TIMER0
  • CNTRL
  • VCTCXO_TAMER

Indices and tables

  • Index

  • Module Index

  • Search Page

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© Copyright 2024-2025, Lime Microsystems. Last updated on Apr 02, 2026.

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