LimeSDR Mini V1 Host Register Reference

This page is generated from CSV sources.

Quick Navigation

Module overview

Module	Address range	Typical use
FPGACFG	0x0000 - 0x001F	Board ID, gateware revision, interface and LMS control
PLLCFG	0x0020 - 0x003F	PLL status/control, divider and counter configuration
TSTCFG	0x0060 - 0x007F	Built-in test control, status, and counters
PERIPHCFG	0x00C0 - 0x00DF	GPIO and peripheral override/readback control

FPGACFG Registers (0x0000 - 0x001F)

FPGACFG registers

Address	Default	Name	Description
0x0000	0x0011	board_id	Board identification number (LimeSDR Mini default 0x0011).
0x0001		gw_ver	Gateware version number.
0x0002		gw_rev	Gateware revision number.
0x0003		board_ver_ctrl	Board BOM version and hardware version.
0x0004	0x0000	-	Reserved.
0x0005	0x0000	drct_clk_en	Clock source selection for RX/TX interfaces.
0x0006	0x0000	-	Reserved.
0x0007	0x0303	ch_en	RX/TX MIMO channel enable control.
0x0008	0x0102	diq_ctrl	DIQ interface control.
0x0009	0x0003	packet_ctrl	Packet control: TX packet-loss clear and timestamp reset.
0x000A	0x0000	rxtx_ctrl	RX/TX module control.
0x000B	0x0000	-	Reserved.
0x000C	0x0003	wfm_ch_en	WFM player channel enable control.
0x000D	0x0001	wfm_ctrl2	WFM player load/play control.
0x000E	0x0002	wfm_smpl_width	WFM player sample width control.
0x000F	0x0000	-	Reserved.
0x0010	0x0000	-	Reserved.
0x0011	0x0000	-	Reserved.
0x0012	0xFFFF	spi_ss	Controlled SPI slave-select enable bits.
0x0013	0x6F6F	lms_misc	LMS7002 MISC pin control.
0x0014	0x0000	-	Reserved for lms3_4.
0x0015	0x0000	-	Reserved for lms5_6.
0x0016	0x0000	-	Reserved for lms7_8.
0x0017	0x0000	gpio	GPIO for external periphery.
0x0018	0x0001	dev_ctrl0	Device control bit 0 (not used).
0x0019		-	Reserved.
0x001A	0x0000	fpga_led_ctrl	Onboard FPGA LED override/control.
0x001B	0x0000	-	Reserved.
0x001C	0x0000	fx3_led_ctrl	Onboard FX3 LED override/control.
0x001D	0x0000	-	Reserved.
0x001E	0x0000	-	Reserved.
0x001F	0x0000	-	Reserved.

PLLCFG Registers (0x0020 - 0x003F)

PLLCFG registers

Address	Default	Name	Description
0x0020	0x0000	-	Reserved.
0x0021	0x0001	pll_status	PLL configuration status.
0x0022	0x0000	pll_lock	RX/TX PLL lock status.
0x0023	0x0000	pll_ctrl	PLL control.
0x0024	0x0000	cnt_phase	Counter phase value.
0x0025	0x01F0	pllcfg_settings	PLL reconfiguration settings.
0x0026	0x0001	mn_bypass_ctrl	M/N counter bypass and odd-division control.
0x0027	0x555A	c0..c7_byp_odddiv	Counter bypass and odd-division control bits for C0..C7.
0x0028	0x5555	c8..c15_byp_odddiv	Counter bypass and odd-division control bits for C8..C15.
0x0029		-	Reserved.
0x002A	0x0000	n_cnt	N counter values.
0x002B	0x0000	m_cnt	M counter values.
0x002C	0x0000	m_frac_l	M fractional counter values [15:0].
0x002D	0x0000	m_frac_h	M fractional counter values [31:16].
0x002E	0x0000	c0_cnt	C0 counter values.
0x002F	0x0000	c1_cnt	C1 counter values.
0x0030	0x0000	c2_cnt	C2 counter values.
0x0031	0x0000	c3_cnt	C3 counter values.
0x0032	0x0000	c4_cnt	C4 counter values.
0x0033	0x0000	c5_cnt	C5 counter values.
0x0034	0x0000	c6_cnt	C6 counter values.
0x0035	0x0000	c7_cnt	C7 counter values.
0x0036	0x0000	c8_cnt	C8 counter values.
0x0037	0x0000	c9_cnt	C9 counter values.
0x0038		-	Reserved for C10..C15 counter values.
0x0039		-	Reserved for C10..C15 counter values.
0x003A		-	Reserved for C10..C15 counter values.
0x003B		-	Reserved for C10..C15 counter values.
0x003C		-	Reserved for C10..C15 counter values.
0x003D		-	Reserved for C10..C15 counter values.
0x003E	0x0FFF	auto_phcfg_smpls	Samples to compare in auto phase-shift mode.
0x003F	0x0002	auto_phcfg_step	Step size for auto phase.

TSTCFG Registers (0x0060 - 0x007F)

TSTCFG registers

Address	Default	Name	Description
0x0060	0x00F0	spi_sign	SPI signature and test register.
0x0061	0x0000	test_en	Test enable controls.
0x0062		-	Reserved.
0x0063	0x0000	test_frc_err	Error insertion controls for tests.
0x0064		-	Reserved.
0x0065	0x0000	test_cmplt	Test completion status bits.
0x0066		-	Reserved.
0x0067	0x0000	test_rez	Test result bits.
0x0068		-	Reserved.
0x0069		fx3_clk_cnt	FX3 PCLK counter value.
0x006A		si5351c_clk0_cnt	Si5351C CLK0 counter value.
0x006B		si5351c_clk1_cnt	Si5351C CLK1 counter value.
0x006C		si5351c_clk2_cnt	Si5351C CLK2 counter value.
0x006D		si5351c_clk3_cnt	Si5351C CLK3 counter value.
0x006E		-	Reserved.
0x006F		si5351c_clk5_cnt	Si5351C CLK5 counter value.
0x0070		si5351c_clk6_cnt	Si5351C CLK6 counter value.
0x0071		si5351c_clk7_cnt	Si5351C CLK7 counter value.
0x0072		lmk_clk_cnt_l	LMK clock counter low word.
0x0073		lmk_clk_cnt_h	LMK clock counter high word.
0x0074		adf_cnt	ADF transition count value.
0x0075		-	Reserved.
0x0076		ddr2_1_tst_detail1	DDR2_1 detailed test result flags.
0x0077		ddr2_1_pnf_per_bit_l	DDR2_1 data [15:0] pass/fail per bit.
0x0078		ddr2_1_pnf_per_bit_h	DDR2_1 data [31:16] pass/fail per bit.
0x0079		-	Reserved.
0x007A		ddr2_2_tst_detail1	DDR2_2 detailed test result flags.
0x007B		ddr2_2_pnf_per_bit_l	DDR2_2 data [15:0] pass/fail per bit.
0x007C		ddr2_2_pnf_per_bit_h	DDR2_2 data [31:16] pass/fail per bit.
0x007D	0xAAAA	tx_tst_i	TX test pattern I sample value.
0x007E	0x5555	tx_tst_q	TX test pattern Q sample value.
0x007F		-	Reserved.

PERIPHCFG Registers (0x00C0 - 0x00DF)

PERIPHCFG registers

Address	Default	Name	Description
0x00C0	0xFFFF	board_gpio_ovrd	Board GPIO override control.
0x00C1		-	Reserved for GPIO.
0x00C2	0x0000	board_gpio_rd	Board GPIO read value.
0x00C3		-	Reserved for GPIO.
0x00C4	0x0000	board_gpio_dir	Board GPIO direction control.
0x00C5		-	Reserved for GPIO.
0x00C6	0x0000	board_gpio_val	Board GPIO output value control.
0x00C7		-	Reserved for GPIO.
0x00C8	0x0000	periph_input_rd_0	Peripheral input readback 0 (not used).
0x00C9	0x0000	periph_input_rd_1	Peripheral input readback 1 (not used).
0x00CA		-	Reserved.
0x00CB		-	Reserved.
0x00CC	0x0000	periph_output_ovrd_0	Peripheral output override 0 (fan).
0x00CD	0x0000	periph_output_val_0	Peripheral output value 0 (fan).
0x00CE	0x0000	periph_output_ovrd_1	Peripheral output override 1 (not used).
0x00CF	0x0000	periph_output_val_1	Peripheral output value 1 (not used).
0x00D0		-	Reserved.
0x00D1		-	Reserved.
0x00D2		-	Reserved.
0x00D3		-	Reserved.
0x00D4		-	Reserved.
0x00D5		-	Reserved.
0x00D6		-	Reserved.
0x00D7		-	Reserved.
0x00D8		-	Reserved.
0x00D9		-	Reserved.
0x00DA		-	Reserved.
0x00DB		-	Reserved.
0x00DC		-	Reserved.
0x00DD		-	Reserved.
0x00DE		-	Reserved.
0x00DF		-	Reserved.

Register Bitfield Reference

Bit fields below are shown from MSB to LSB where applicable.

0x0000 - board_id

Address: 0x0000 | Default: 0x0011 | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	board_id		Board identification number (LimeSDR Mini default 0x0011).

0x0001 - gw_ver

Address: 0x0001 | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	gw_ver		Gateware version number.

0x0002 - gw_rev

Address: 0x0002 | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	gw_rev		Gateware revision number.

0x0003 - board_ver_ctrl

Address: 0x0003 | Default: not specified | Access: R

Bit(s)	Field	Values	Description
[6:4]	bom_ver		Bill of material version.
[3:0]	hw_ver		Hardware version.

0x0004 - reserved

Address: 0x0004 | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x0005 - drct_clk_en

Address: 0x0005 | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[1]	drct_clk_en_rx	0=PLL,1=Direct	RX clock source selection.
[0]	drct_clk_en_tx	0=PLL,1=Direct	TX clock source selection.

0x0006 - reserved

Address: 0x0006 | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x0007 - ch_en

Address: 0x0007 | Default: 0x0303 | Access: R/W

Bit(s)	Field	Values	Description
[9]	ch_en_tx1	0=Disabled,1=Enabled	TX channel 1 enable.
[8]	ch_en_tx0	0=Disabled,1=Enabled	TX channel 0 enable.
[1]	ch_en_rx1	0=Disabled,1=Enabled	RX channel 1 enable.
[0]	ch_en_rx0	0=Disabled,1=Enabled	RX channel 0 enable.

0x0008 - diq_ctrl

Address: 0x0008 | Default: 0x0102 | Access: R/W

Bit(s)	Field	Values	Description
[10]	dlb_en	0=Disabled,1=Enabled	Loopback enable (not used).
[9]	synch_dis	0=Enabled,1=Disabled	Packet synchronization using timestamps.
[8]	mimo_int_en	0=Disabled,1=Enabled	MIMO mode control.
[7]	triq_pulse	0=OFF,1=ON	TRXIQ pulse mode.
[6]	ddr_en	0=SDR,1=DDR	DIQ interface mode.
[5]	mode	0=TRXIQ,1=JESD207	Limelight port mode (JESD207 not implemented).
[1:0]	smpl_width	10=12-bit,00=16-bit	Interface sample width selection.

0x0009 - packet_ctrl

Address: 0x0009 | Default: 0x0003 | Access: R/W

Bit(s)	Field	Values	Description
[1]	txpct_loss_clr	0=Normal,1=Rising edge clears	TX packet dropping flag clear.
[0]	smpl_nr_clr	0=Normal,1=Clear	Timestamp reset control.

0x000A - rxtx_ctrl

Address: 0x000A | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[9]	tx_ptrn_en	0=Disabled,1=Enabled	TX test pattern enable.
[8]	rx_ptrn_en	0=Disabled,1=Enabled	RX test pattern enable.
[1]	tx_en	0=Disabled,1=Enabled	TX chain enable.
[0]	rx_en	0=Disabled,1=Enabled	RX chain enable.

0x000B - reserved

Address: 0x000B | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x000C - wfm_ch_en

Address: 0x000C | Default: 0x0003 | Access: R/W

Bit(s)	Field	Values	Description
[1]	wfm_ch1_en	0=Disabled,1=Enabled	WFM channel 1 enable.
[0]	wfm_ch0_en	0=Disabled,1=Enabled	WFM channel 0 enable.

0x000D - wfm_ctrl2

Address: 0x000D | Default: 0x0001 | Access: R/W

Bit(s)	Field	Values	Description
[2]	wfm_load	0->1 transition	Starts WFM file loading.
[1]	wfm_play	0=Disabled,1=Enabled	WFM loaded-file play enable.

0x000E - wfm_smpl_width

Address: 0x000E | Default: 0x0002 | Access: R/W

Bit(s)	Field	Values	Description
[1:0]	wfm_smpl_width	10=12-bit,00=16-bit	WFM sample width selection.

0x000F - reserved

Address: 0x000F | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x0010 - reserved

Address: 0x0010 | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x0011 - reserved

Address: 0x0011 | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x0012 - spi_ss

Address: 0x0012 | Default: 0xFFFF | Access: R/W

Bit(s)	Field	Values	Description
[7:0]	spi_ss		Controlled SPI slave-select bits.

0x0013 - lms_misc

Address: 0x0013 | Default: 0x6F6F | Access: R/W

Bit(s)	Field	Values	Description
[6]	lms1_rxen	0=Disabled,1=Enabled	LMS1 RX hard enable.
[5]	lms1_txen	0=Disabled,1=Enabled	LMS1 TX hard enable.
[4]	lms1_txnrx2	0=TXIQ,1=RXIQ	LMS1 port 2 mode.
[3]	lms1_txnrx1	0=TXIQ,1=RXIQ	LMS1 port 1 mode.
[2]	lms1_core_ldo_en	0=Disabled,1=Enabled	LMS1 internal LDO control.
[1]	lms1_reset	0=Reset active,1=Inactive	LMS1 hardware reset.

0x0014 - reserved

Address: 0x0014 | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved for lms3_4.

0x0015 - reserved

Address: 0x0015 | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved for lms5_6.

0x0016 - reserved

Address: 0x0016 | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved for lms7_8.

0x0017 - gpio

Address: 0x0017 | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[6]	gpio6	0=Disabled,1=Enabled	Channel B shunt.
[5]	gpio5	0=Disabled,1=Enabled	Channel B attenuator.
[4]	gpio4	0=Disabled,1=Enabled	RF loopback channel B.
[2]	gpio2	0=Disabled,1=Enabled	Channel A shunt.
[1]	gpio1	0=Disabled,1=Enabled	Channel A attenuator.
[0]	gpio0	0=Disabled,1=Enabled	RF loopback channel A.

0x0018 - dev_ctrl0

Address: 0x0018 | Default: 0x0001 | Access: R/W

Bit(s)	Field	Values	Description
[0]	dev_ctrl0		Device control bit (not used).

0x0019 - reserved

Address: 0x0019 | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x001A - fpga_led_ctrl

Address: 0x001A | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[6]	fpga_led2_g	0=OFF,1=ON	Green LED2 control.
[5]	fpga_led2_r	0=OFF,1=ON	Red LED2 control.
[4]	fpga_led2_ovrd	0=OFF,1=ON	LED2 control override.
[2]	fpga_led1_g	0=OFF,1=ON	Green LED1 control.
[1]	fpga_led1_r	0=OFF,1=ON	Red LED1 control.
[0]	fpga_led1_ovrd	0=OFF,1=ON	LED1 control override.

0x001B - reserved

Address: 0x001B | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x001C - fx3_led_ctrl

Address: 0x001C | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[2]	fx3_led_g	0=OFF,1=ON	Green FX3 LED control.
[1]	fx3_led_r	0=OFF,1=ON	Red FX3 LED control.
[0]	fx3_led_ovrd	0=OFF,1=ON	FX3 LED override.

0x001D - reserved

Address: 0x001D | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x001E - reserved

Address: 0x001E | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x001F - reserved

Address: 0x001F | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x0020 - reserved

Address: 0x0020 | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x0021 - pll_status

Address: 0x0021 | Default: 0x0001 | Access: R

Bit(s)	Field	Values	Description
[3]	auto_phcfg_err	0=No error,1=Error	Auto phase configuration error status.
[2]	auto_phcfg_done	0=Not done,1=Done	Auto phase configuration done status.
[1]	busy	0=Idle,1=Busy	PLL reconfiguration busy status.
[0]	done	0=Not done,1=Done	PLL configuration done status.

0x0022 - pll_lock

Address: 0x0022 | Default: 0x0000 | Access: R

Bit(s)	Field	Values	Description
[1]	pll_lock_rx	0=No lock,1=Locked	RX PLL lock.
[0]	pll_lock_tx	0=No lock,1=Locked	TX PLL lock.

0x0023 - pll_ctrl

Address: 0x0023 | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[14]	phcfg_mode	0=Manual,1=AUTO	PLL phase configuration mode.
[13]	phcfg_updn	0=Down,1=Up	Phase shift direction.
[12:8]	cnt_ind	0000=all,0001=M,0010=C0,0011=C1	Counter index for phase shift.
[7:3]	pll_ind	0000=TX PLL,0001=RX PLL	PLL index for reconfiguration.
[2]	pllrst_start	0->1 transition	PLL reset trigger.
[1]	phcfg_start	0->1 transition	Phase shift start trigger.
[0]	pllcfg_start	0->1 transition	PLL reconfiguration start trigger.

0x0024 - cnt_phase

Address: 0x0024 | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	cnt_phase		Counter phase value.

0x0025 - pllcfg_settings

Address: 0x0025 | Default: 0x01F0 | Access: R/W

Bit(s)	Field	Values	Description
[14:11]	pllcfg_bs		Bandwidth setting (not used).
[10:8]	chp_curr		PLL charge pump current.
[7]	pllcfg_vcodiv	0=2,1=1	PLL VCO division value.
[6:2]	pllcfg_lf_res		PLL loop filter resistance.
[1:0]	pllcfg_lf_cap		PLL loop filter capacitance.

0x0026 - mn_bypass_ctrl

Address: 0x0026 | Default: 0x0001 | Access: R/W

Bit(s)	Field	Values	Description
[3]	m_byp	0=normal,1=bypass	M counter bypass control.
[2]	m_odddiv	0=even,1=odd	M counter odd-division enable.
[1]	n_byp	0=normal,1=bypass	N counter bypass control.
[0]	n_odddiv	0=even,1=odd	N counter odd-division enable.

0x0027 - c0..c7_byp_odddiv

Address: 0x0027 | Default: 0x555A | Access: R/W

Bit(s)	Field	Values	Description
[15]	c7_byp	0=normal,1=bypass	C7 bypass control.
[14]	c7_odddiv	0=even,1=odd	C7 odd-division enable.
[13]	c6_byp	0=normal,1=bypass	C6 bypass control.
[12]	c6_odddiv	0=even,1=odd	C6 odd-division enable.
[11]	c5_byp	0=normal,1=bypass	C5 bypass control.
[10]	c5_odddiv	0=even,1=odd	C5 odd-division enable.
[9]	c4_byp	0=normal,1=bypass	C4 bypass control.
[8]	c4_odddiv	0=even,1=odd	C4 odd-division enable.
[7]	c3_byp	0=normal,1=bypass	C3 bypass control.
[6]	c3_odddiv	0=even,1=odd	C3 odd-division enable.
[5]	c2_byp	0=normal,1=bypass	C2 bypass control.
[4]	c2_odddiv	0=even,1=odd	C2 odd-division enable.
[3]	c1_byp	0=normal,1=bypass	C1 bypass control.
[2]	c1_odddiv	0=even,1=odd	C1 odd-division enable.
[1]	c0_byp	0=normal,1=bypass	C0 bypass control.
[0]	c0_odddiv	0=even,1=odd	C0 odd-division enable.

0x0028 - c8..c15_byp_odddiv

Address: 0x0028 | Default: 0x5555 | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	c8..c15_byp_odddiv		Counter bypass and odd-division control bits for C8..C15.

0x0029 - reserved

Address: 0x0029 | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x002A - n_cnt

Address: 0x002A | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[15:8]	n_hcnt		N_CNT high counter bits.
[7:0]	n_lcnt		N_CNT low counter bits.

0x002B - m_cnt

Address: 0x002B | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[15:8]	m_hcnt		M_CNT high counter bits.
[7:0]	m_lcnt		M_CNT low counter bits.

0x002C - m_frac_l

Address: 0x002C | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	m_frac_l		M fractional counter values [15:0].

0x002D - m_frac_h

Address: 0x002D | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	m_frac_h		M fractional counter values [31:16].

0x002E - c0_cnt

Address: 0x002E | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[15:8]	c0_hcnt		C0_CNT high counter bits.
[7:0]	c0_lcnt		C0_CNT low counter bits.

0x002F - c1_cnt

Address: 0x002F | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[15:8]	c1_hcnt		C1_CNT high counter bits.
[7:0]	c1_lcnt		C1_CNT low counter bits.

0x0030 - c2_cnt

Address: 0x0030 | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[15:8]	c2_hcnt		C2_CNT high counter bits.
[7:0]	c2_lcnt		C2_CNT low counter bits.

0x0031 - c3_cnt

Address: 0x0031 | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[15:8]	c3_hcnt		C3_CNT high counter bits.
[7:0]	c3_lcnt		C3_CNT low counter bits.

0x0032 - c4_cnt

Address: 0x0032 | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[15:8]	c4_hcnt		C4_CNT high counter bits.
[7:0]	c4_lcnt		C4_CNT low counter bits.

0x0033 - c5_cnt

Address: 0x0033 | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[15:8]	c5_hcnt		C5_CNT high counter bits.
[7:0]	c5_lcnt		C5_CNT low counter bits.

0x0034 - c6_cnt

Address: 0x0034 | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[15:8]	c6_hcnt		C6_CNT high counter bits.
[7:0]	c6_lcnt		C6_CNT low counter bits.

0x0035 - c7_cnt

Address: 0x0035 | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[15:8]	c7_hcnt		C7_CNT high counter bits.
[7:0]	c7_lcnt		C7_CNT low counter bits.

0x0036 - c8_cnt

Address: 0x0036 | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[15:8]	c8_hcnt		C8_CNT high counter bits.
[7:0]	c8_lcnt		C8_CNT low counter bits.

0x0037 - c9_cnt

Address: 0x0037 | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[15:8]	c9_hcnt		C9_CNT high counter bits.
[7:0]	c9_lcnt		C9_CNT low counter bits.

0x0038 - reserved

Address: 0x0038 | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved for C10..C15 counter values.

0x0039 - reserved

Address: 0x0039 | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved for C10..C15 counter values.

0x003A - reserved

Address: 0x003A | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved for C10..C15 counter values.

0x003B - reserved

Address: 0x003B | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved for C10..C15 counter values.

0x003C - reserved

Address: 0x003C | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved for C10..C15 counter values.

0x003D - reserved

Address: 0x003D | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved for C10..C15 counter values.

0x003E - auto_phcfg_smpls

Address: 0x003E | Default: 0x0FFF | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	auto_phcfg_smpls		Samples to compare in auto phase-shift mode.

0x003F - auto_phcfg_step

Address: 0x003F | Default: 0x0002 | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	auto_phcfg_step		Step size for auto phase.

0x0060 - spi_sign

Address: 0x0060 | Default: 0x00F0 | Access: R/W

Bit(s)	Field	Values	Description
[7:4]	spi_sign_rezult		Inverted bits from SPI_SIGN register.
[3:0]	spi_sign		SPI module test register.

0x0061 - test_en

Address: 0x0061 | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[5]	ddr2_2_tst_en	0=Disabled,1=Enabled	DDR2_2 memory test enable.
[4]	ddr2_1_tst_en	0=Disabled,1=Enabled	DDR2_1 memory test enable.
[3]	adf_tst_en	0=Disabled,1=Enabled	Phase detector test enable.
[2]	vctcxo_tst_en	0=Disabled,1=Enabled	VCTCXO test enable.
[1]	si5351c_tst_en	0=Disabled,1=Enabled	Si5351C clock test enable.
[0]	fx3_pclk_tst_en	0=Disabled,1=Enabled	FX3 PCLK test enable.

0x0062 - reserved

Address: 0x0062 | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x0063 - test_frc_err

Address: 0x0063 | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[5]	ddr2_2_tst_frc_err	0=Disabled,1=Enabled	Insert error to DDR2_2 memory test.
[4]	ddr2_1_tst_frc_err	0=Disabled,1=Enabled	Insert error to DDR2_1 memory test.
[3]	adf_tst_frc_err	0=Disabled,1=Enabled	Insert error to phase detector test.
[2]	vctcxo_tst_frc_err	0=Disabled,1=Enabled	Insert error to VCTCXO test.
[1]	si5351c_tst_frc_err	0=Disabled,1=Enabled	Insert error to Si5351C test.
[0]	fx3_pclk_tst_frc_err	0=Disabled,1=Enabled	Insert error to FX3 PCLK test.

0x0064 - reserved

Address: 0x0064 | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x0065 - test_cmplt

Address: 0x0065 | Default: 0x0000 | Access: R

Bit(s)	Field	Values	Description
[5]	ddr2_2_tst_cmplt	0=Not completed,1=Completed	DDR2_2 test complete status.
[4]	ddr2_1_tst_cmplt	0=Not completed,1=Completed	DDR2_1 test complete status.
[3]	adf_tst_cmplt	0=Not completed,1=Completed	Phase detector test complete status.
[2]	vctcxo_tst_cmplt	0=Not completed,1=Completed	VCTCXO test complete status.
[1]	si5351c_tst_cmplt	0=Not completed,1=Completed	Si5351C test complete status.
[0]	fx3_pclk_tst_cmplt	0=Not completed,1=Completed	FX3 PCLK test complete status.

0x0066 - reserved

Address: 0x0066 | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x0067 - test_rez

Address: 0x0067 | Default: 0x0000 | Access: R

Bit(s)	Field	Values	Description
[5]	ddr2_2_tst_rez		DDR2_2 test result.
[4]	ddr2_1_tst_rez		DDR2_1 test result.
[3]	adf_tst_rez		Not used.
[2]	vctcxo_tst_rez		Not used.
[1]	si5351c_tst_rez		Not used.
[0]	fx3_pclk_tst_rez		Not used.

0x0068 - reserved

Address: 0x0068 | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x0069 - fx3_clk_cnt

Address: 0x0069 | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	fx3_clk_cnt		FX3 PCLK counter value.

0x006A - si5351c_clk0_cnt

Address: 0x006A | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	si5351c_clk0_cnt		Si5351C CLK0 counter value.

0x006B - si5351c_clk1_cnt

Address: 0x006B | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	si5351c_clk1_cnt		Si5351C CLK1 counter value.

0x006C - si5351c_clk2_cnt

Address: 0x006C | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	si5351c_clk2_cnt		Si5351C CLK2 counter value.

0x006D - si5351c_clk3_cnt

Address: 0x006D | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	si5351c_clk3_cnt		Si5351C CLK3 counter value.

0x006E - reserved

Address: 0x006E | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x006F - si5351c_clk5_cnt

Address: 0x006F | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	si5351c_clk5_cnt		Si5351C CLK5 counter value.

0x0070 - si5351c_clk6_cnt

Address: 0x0070 | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	si5351c_clk6_cnt		Si5351C CLK6 counter value.

0x0071 - si5351c_clk7_cnt

Address: 0x0071 | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	si5351c_clk7_cnt		Si5351C CLK7 counter value.

0x0072 - lmk_clk_cnt_l

Address: 0x0072 | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	lmk_clk_cnt_l		LMK clock counter low word.

0x0073 - lmk_clk_cnt_h

Address: 0x0073 | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	lmk_clk_cnt_h		LMK clock counter high word.

0x0074 - adf_cnt

Address: 0x0074 | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	adf_cnt		ADF transition count value.

0x0075 - reserved

Address: 0x0075 | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x0076 - ddr2_1_tst_detail1

Address: 0x0076 | Default: not specified | Access: R

Bit(s)	Field	Values	Description
[2]	ddr2_1_tst_fail	0=Not completed,1=Fail	DDR2_1 fail flag.
[1]	ddr2_1_tst_pass	0=Not completed,1=Pass	DDR2_1 pass flag.
[0]	ddr2_1_tst_cmplt	0=Not completed,1=Complete	DDR2_1 complete flag.

0x0077 - ddr2_1_pnf_per_bit_l

Address: 0x0077 | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	ddr2_1_pnf_per_bit_l		DDR2_1 data [15:0] pass/fail per bit.

0x0078 - ddr2_1_pnf_per_bit_h

Address: 0x0078 | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	ddr2_1_pnf_per_bit_h		DDR2_1 data [31:16] pass/fail per bit.

0x0079 - reserved

Address: 0x0079 | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x007A - ddr2_2_tst_detail1

Address: 0x007A | Default: not specified | Access: R

Bit(s)	Field	Values	Description
[2]	ddr2_2_tst_fail	0=Not completed,1=Fail	DDR2_2 fail flag.
[1]	ddr2_2_tst_pass	0=Not completed,1=Pass	DDR2_2 pass flag.
[0]	ddr2_2_tst_cmplt	0=Not completed,1=Complete	DDR2_2 complete flag.

0x007B - ddr2_2_pnf_per_bit_l

Address: 0x007B | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	ddr2_2_pnf_per_bit_l		DDR2_2 data [15:0] pass/fail per bit.

0x007C - ddr2_2_pnf_per_bit_h

Address: 0x007C | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	ddr2_2_pnf_per_bit_h		DDR2_2 data [31:16] pass/fail per bit.

0x007D - tx_tst_i

Address: 0x007D | Default: 0xAAAA | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	tx_tst_i		TX test pattern I sample value.

0x007E - tx_tst_q

Address: 0x007E | Default: 0x5555 | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	tx_tst_q		TX test pattern Q sample value.

0x007F - reserved

Address: 0x007F | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x00C0 - board_gpio_ovrd

Address: 0x00C0 | Default: 0xFFFF | Access: R/W

Bit(s)	Field	Values	Description
[7:0]	board_gpio_ovrd	0=Dedicated function,1=Overridden by user	GPIO override bits.

0x00C1 - reserved

Address: 0x00C1 | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved for GPIO.

0x00C2 - board_gpio_rd

Address: 0x00C2 | Default: 0x0000 | Access: R

Bit(s)	Field	Values	Description
[7:0]	board_gpio_rd	0=Low,1=High	GPIO readback bits.

0x00C3 - reserved

Address: 0x00C3 | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved for GPIO.

0x00C4 - board_gpio_dir

Address: 0x00C4 | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[7:0]	board_gpio_dir	0=Input,1=Output	GPIO direction bits.

0x00C5 - reserved

Address: 0x00C5 | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved for GPIO.

0x00C6 - board_gpio_val

Address: 0x00C6 | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[7:0]	board_gpio_val	0=Low,1=High	GPIO output value bits.

0x00C7 - reserved

Address: 0x00C7 | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved for GPIO.

0x00C8 - periph_input_rd_0

Address: 0x00C8 | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	periph_input_rd_0		Peripheral input readback 0 (not used).

0x00C9 - periph_input_rd_1

Address: 0x00C9 | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	periph_input_rd_1		Peripheral input readback 1 (not used).

0x00CA - reserved

Address: 0x00CA | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x00CB - reserved

Address: 0x00CB | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x00CC - periph_output_ovrd_0

Address: 0x00CC | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[0]	periph_output_ovrd_0	0=Dedicated,1=User controlled	Fan control override.

0x00CD - periph_output_val_0

Address: 0x00CD | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[0]	periph_output_val_0	0=OFF,1=ON	Fan control pin value.

0x00CE - periph_output_ovrd_1

Address: 0x00CE | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	periph_output_ovrd_1		Peripheral output override 1 (not used).

0x00CF - periph_output_val_1

Address: 0x00CF | Default: 0x0000 | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	periph_output_val_1		Peripheral output value 1 (not used).

0x00D0 - reserved

Address: 0x00D0 | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x00D1 - reserved

Address: 0x00D1 | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x00D2 - reserved

Address: 0x00D2 | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x00D3 - reserved

Address: 0x00D3 | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x00D4 - reserved

Address: 0x00D4 | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x00D5 - reserved

Address: 0x00D5 | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x00D6 - reserved

Address: 0x00D6 | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x00D7 - reserved

Address: 0x00D7 | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x00D8 - reserved

Address: 0x00D8 | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x00D9 - reserved

Address: 0x00D9 | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x00DA - reserved

Address: 0x00DA | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x00DB - reserved

Address: 0x00DB | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x00DC - reserved

Address: 0x00DC | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x00DD - reserved

Address: 0x00DD | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x00DE - reserved

Address: 0x00DE | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.

0x00DF - reserved

Address: 0x00DF | Default: not specified | Access: R/W

Bit(s)	Field	Values	Description
[15:0]	-		Reserved.