HiperSDR 44xx
This section provides detailed information about the gateware implemented for the HiperSDR 44xx board.
Main Block Diagram
The top-level file integrates the following main blocks:
Soft core CPU – VexRiscv CPU instance.
AFE79xx – RF Transceiver instance.
LimeTop Module – Wrapper for blocks handling RF transceiver control and data transfer.
PCIe PHY – PCIe block with the physical interface and DMA.
I2C0, I2C1, I2C2, I2C3 – I2C Communication interfaces for controlling onboard peripherals.
SPI0, SPI1, SPI2, – SPI Communication interfaces for controlling onboard peripherals.
USSPI Flash – Module for accessing the FPGA configuration FLASH memory.
Soft core CPU Module
The CPU module is a vexriscv_smp core provided by LiteX. It is specified via the cpu_type parameter for the SoCCore class, which serves as the parent class for the top-level gateware design.
The source code for the CPU can be found at: LiteX VexRiscv SMP core
AFE79xx
This module is part of LimeDFB and more details can be found in description. It interfaces with TI JESD IP to exchange sample data with the AFE7901 chip. It also performs resampling, clock domain crossing and aligns the data for proper integration with other LimeDFB modules.
LimeTop Module
The LimeTop Module serves as a wrapper for the RF transceiver control and data transfer blocks. Its main sub-blocks include:
RX Path Top Module – Manages the receive path from the RF transceiver to the FPGA and host, packing IQ samples into packets and generating timestamps.
TX Path Top Module – Manages the transmit path from the host through the FPGA to the RF transceiver, unpacking IQ sample packets and handling stream synchronization with timestamps.
RX Path Top Module
This module is part of LimeDFB and more details can be found in description. It handles the receive path from the RF Transceiver to the FPGA and host, including IQ sample packetization and timestamp generation.
TX Path Top Module
This module is part of LimeDFB and more details can be found in description. This module manages the transmit path from the host through the FPGA to the RF Transceiver, including unpacking of IQ samples and stream synchronization.
PCIe PHY Module
The PCIe PHY module is an instantiation of the USPPCIEPHY class from LitePCIe. It provides the physical layer for the PCIe interface, including DMA support.
The source code for LitePCIe is available at: LitePCIe on GitHub
I2C Modules
The I2C0, I2C1, I2C2, I2C3 modules are instances of the I2CMaster class provided by LiteX. They are used for controlling onboard peripherals via the I2C protocol.
The source code can be found here: I2CMaster in LiteX
SPI Modules
The SPI0, SPI1, SPI2 modules are an instantiation of the SPIMaster class from LiteX. It handles SPI communication with the LMS8001, AFE7901 and ADF4002 ICs.
Source code: SPIMaster in LiteX
Flash Module
The Flash module is implemented using the USSPIFlash class provided by LiteX. It enables access to the FPGA configuration FLASH memory.
Source code: USSPIFlash in LiteX
HiperSDR_44xx RF controls
HiperSDR_44xx board utilises over a hundred GPIO signals to all of the RF elements present on the board. The mapping of the GPIO signals to the onboard elements can be seen in the diagram provided below:
Gateware Register Reference
The following documentation is automatically generated from the LiteX SoC definitions. It includes the complete Control and Status Register (CSR) map, interrupt vector table, and memory regions for the modules described above (PCIe, I2C, SPI, etc.).