PCIE_DMA0

Register Listing for PCIE_DMA0

Register	Address
PCIE_DMA0_WRITER_ENABLE	0xf0002800
PCIE_DMA0_WRITER_TABLE_VALUE1	0xf0002804
PCIE_DMA0_WRITER_TABLE_VALUE0	0xf0002808
PCIE_DMA0_WRITER_TABLE_WE	0xf000280c
PCIE_DMA0_WRITER_TABLE_LOOP_PROG_N	0xf0002810
PCIE_DMA0_WRITER_TABLE_LOOP_STATUS	0xf0002814
PCIE_DMA0_WRITER_TABLE_LEVEL	0xf0002818
PCIE_DMA0_WRITER_TABLE_RESET	0xf000281c
PCIE_DMA0_READER_ENABLE	0xf0002820
PCIE_DMA0_READER_TABLE_VALUE1	0xf0002824
PCIE_DMA0_READER_TABLE_VALUE0	0xf0002828
PCIE_DMA0_READER_TABLE_WE	0xf000282c
PCIE_DMA0_READER_TABLE_LOOP_PROG_N	0xf0002830
PCIE_DMA0_READER_TABLE_LOOP_STATUS	0xf0002834
PCIE_DMA0_READER_TABLE_LEVEL	0xf0002838
PCIE_DMA0_READER_TABLE_RESET	0xf000283c
PCIE_DMA0_BUFFERING_READER_FIFO_CONTROL	0xf0002840
PCIE_DMA0_BUFFERING_READER_FIFO_STATUS	0xf0002844
PCIE_DMA0_BUFFERING_WRITER_FIFO_CONTROL	0xf0002848
PCIE_DMA0_BUFFERING_WRITER_FIFO_STATUS	0xf000284c

PCIE_DMA0_WRITER_ENABLE

Address: 0xf0002800 + 0x0 = 0xf0002800

DMA Writer Control. Write 1 to enable DMA Writer.

PCIE_DMA0_WRITER_TABLE_VALUE1

Address: 0xf0002800 + 0x4 = 0xf0002804

Bits 32-57 of PCIE_DMA0_WRITER_TABLE_VALUE. 64-bit DMA descriptor to be written to the table.

Field	Name	Description
[23:0]	LENGTH	24-bit Length of the descriptor (in bytes).
[24]	IRQ_DISABLE	IRQ Disable Control of the descriptor.
[25]	LAST_DISABLE	Last Disable Control of the descriptor.

PCIE_DMA0_WRITER_TABLE_VALUE0

Address: 0xf0002800 + 0x8 = 0xf0002808

Bits 0-31 of PCIE_DMA0_WRITER_TABLE_VALUE.

Field	Name	Description
[31:0]	ADDRESS_LSB	32-bit LSB Address of the descriptor (bytes-aligned).

PCIE_DMA0_WRITER_TABLE_WE

Address: 0xf0002800 + 0xc = 0xf000280c

Write and 32-bit MSB Address of the descriptor (bytes-aligned)

Field	Name	Description
[31:0]	ADDRESS_MSB	32-bit MSB Address of the descriptor (bytes-aligned), in 64-bit mode.

PCIE_DMA0_WRITER_TABLE_LOOP_PROG_N

Address: 0xf0002800 + 0x10 = 0xf0002810

Mode Selection.

0: Prog mode / 1: Loop mode.

Prog mode should be used to program the table by software and for cases where automatic refill of the table is not needed: A descriptor is only executed once and when all the descriptors have been executed (ie the table is empty), the DMA just stops until the next software refill.

Loop mode should be used once the table has been filled by software in Prog mode and allow continuous Scatter-Gather DMA: Each descriptor sent to the DMA is refilled to the table.

PCIE_DMA0_WRITER_TABLE_LOOP_STATUS

Address: 0xf0002800 + 0x14 = 0xf0002814

Loop monitoring for software synchronization.

Field	Name	Description
[15:0]	INDEX	Index of the last descriptor executed in the DMA descriptor table.
[31:16]	COUNT	Loops of the DMA descriptor table since started.

PCIE_DMA0_WRITER_TABLE_LEVEL

Address: 0xf0002800 + 0x18 = 0xf0002818

Number descriptors in the table.

PCIE_DMA0_WRITER_TABLE_RESET

Address: 0xf0002800 + 0x1c = 0xf000281c

A write to this register resets the table.

PCIE_DMA0_READER_ENABLE

Address: 0xf0002800 + 0x20 = 0xf0002820

DMA Reader Control. Write 1 to enable DMA Reader.

PCIE_DMA0_READER_TABLE_VALUE1

Address: 0xf0002800 + 0x24 = 0xf0002824

Bits 32-57 of PCIE_DMA0_READER_TABLE_VALUE. 64-bit DMA descriptor to be written to the table.

Field	Name	Description
[23:0]	LENGTH	24-bit Length of the descriptor (in bytes).
[24]	IRQ_DISABLE	IRQ Disable Control of the descriptor.
[25]	LAST_DISABLE	Last Disable Control of the descriptor.

PCIE_DMA0_READER_TABLE_VALUE0

Address: 0xf0002800 + 0x28 = 0xf0002828

Bits 0-31 of PCIE_DMA0_READER_TABLE_VALUE.

Field	Name	Description
[31:0]	ADDRESS_LSB	32-bit LSB Address of the descriptor (bytes-aligned).

PCIE_DMA0_READER_TABLE_WE

Address: 0xf0002800 + 0x2c = 0xf000282c

Write and 32-bit MSB Address of the descriptor (bytes-aligned)

Field	Name	Description
[31:0]	ADDRESS_MSB	32-bit MSB Address of the descriptor (bytes-aligned), in 64-bit mode.

PCIE_DMA0_READER_TABLE_LOOP_PROG_N

Address: 0xf0002800 + 0x30 = 0xf0002830

Mode Selection.

0: Prog mode / 1: Loop mode.

Prog mode should be used to program the table by software and for cases where automatic refill of the table is not needed: A descriptor is only executed once and when all the descriptors have been executed (ie the table is empty), the DMA just stops until the next software refill.

Loop mode should be used once the table has been filled by software in Prog mode and allow continuous Scatter-Gather DMA: Each descriptor sent to the DMA is refilled to the table.

PCIE_DMA0_READER_TABLE_LOOP_STATUS

Address: 0xf0002800 + 0x34 = 0xf0002834

Loop monitoring for software synchronization.

Field	Name	Description
[15:0]	INDEX	Index of the last descriptor executed in the DMA descriptor table.
[31:16]	COUNT	Loops of the DMA descriptor table since started.

PCIE_DMA0_READER_TABLE_LEVEL

Address: 0xf0002800 + 0x38 = 0xf0002838

Number descriptors in the table.

PCIE_DMA0_READER_TABLE_RESET

Address: 0xf0002800 + 0x3c = 0xf000283c

A write to this register resets the table.

PCIE_DMA0_BUFFERING_READER_FIFO_CONTROL

Address: 0xf0002800 + 0x40 = 0xf0002840

Field

Name

Description

[23:0]

DEPTH

DMA Reader FIFO depth (in 64-bit words).

[27:24]

SCRATCH

Software Scratchpad.

[31]

LEVEL_MODE

Value	Description
`0b0`	Report Instantaneous level.
`0b1`	Report Minimal level since last clear.

PCIE_DMA0_BUFFERING_READER_FIFO_STATUS

Address: 0xf0002800 + 0x44 = 0xf0002844

Field	Name	Description
[23:0]	LEVEL	DMA Reader FIFO level (in 64-bit words).

PCIE_DMA0_BUFFERING_WRITER_FIFO_CONTROL

Address: 0xf0002800 + 0x48 = 0xf0002848