LIME_TOP
Register Listing for LIME_TOP
Register |
Address |
|---|---|
LIME_TOP_EV_STATUS |
0xf0006000 |
LIME_TOP_EV_PENDING |
0xf0006004 |
LIME_TOP_EV_ENABLE |
0xf0006008 |
LIME_TOP_GPO |
0xf000600c |
LIME_TOP_FPGACFG_BOARD_ID |
0xf0006010 |
LIME_TOP_FPGACFG_MAJOR_REV |
0xf0006014 |
LIME_TOP_FPGACFG_COMPILE_REV |
0xf0006018 |
LIME_TOP_FPGACFG_RESERVED_03 |
0xf000601c |
LIME_TOP_FPGACFG_RESERVED_04 |
0xf0006020 |
LIME_TOP_FPGACFG_RESERVED_05 |
0xf0006024 |
LIME_TOP_FPGACFG_RESERVED_06 |
0xf0006028 |
LIME_TOP_FPGACFG_CH_EN |
0xf000602c |
LIME_TOP_FPGACFG_REG08 |
0xf0006030 |
LIME_TOP_FPGACFG_REG09 |
0xf0006034 |
LIME_TOP_FPGACFG_REG10 |
0xf0006038 |
LIME_TOP_FPGACFG_WFM_CH_EN |
0xf000603c |
LIME_TOP_FPGACFG_REG13 |
0xf0006040 |
LIME_TOP_FPGACFG_WFM_SMPL_WIDTH |
0xf0006044 |
LIME_TOP_FPGACFG_SYNC_SIZE |
0xf0006048 |
LIME_TOP_FPGACFG_TXANT_PRE |
0xf000604c |
LIME_TOP_FPGACFG_TXANT_POST |
0xf0006050 |
LIME_TOP_FPGACFG_REG18 |
0xf0006054 |
LIME_TOP_FPGACFG_CLK_ENA |
0xf0006058 |
LIME_TOP_FPGACFG_SYNC_PULSE_PERIOD |
0xf000605c |
LIME_TOP_RXTX_TOP_DDR2_1_STATUS |
0xf0006060 |
LIME_TOP_RXTX_TOP_DDR2_1_PNF_PER_BIT_L |
0xf0006064 |
LIME_TOP_RXTX_TOP_DDR2_1_PNF_PER_BIT_H |
0xf0006068 |
LIME_TOP_RXTX_TOP_RX_PATH_PKT_SIZE |
0xf000606c |
LIME_TOP_EV_STATUS
Address: 0xf0006000 + 0x0 = 0xf0006000
This register contains the current raw level of the clk_ctrl_irq event trigger. Writes to this register have no effect.
Field |
Name |
Description |
|---|---|---|
[0] |
CLK_CTRL_IRQ |
Level of the |
LIME_TOP_EV_PENDING
Address: 0xf0006000 + 0x4 = 0xf0006004
When a clk_ctrl_irq event occurs, the corresponding bit will be set in this register. To clear the Event, set the corresponding bit in this register.
Field |
Name |
Description |
|---|---|---|
[0] |
CLK_CTRL_IRQ |
1 if a clk_ctrl_irq event occurred. This Event is triggered on falling edge. |
LIME_TOP_EV_ENABLE
Address: 0xf0006000 + 0x8 = 0xf0006008
This register enables the corresponding clk_ctrl_irq events. Write a
0to this register to disable individual events.
Field |
Name |
Description |
|---|---|---|
[0] |
CLK_CTRL_IRQ |
Write a |
LIME_TOP_GPO
Address: 0xf0006000 + 0xc = 0xf000600c
GPO interface
Field |
Name |
Description |
||||||
|---|---|---|---|---|---|---|---|---|
[0] |
CPU_BUSY |
CPU state.
|
LIME_TOP_FPGACFG_BOARD_ID
Address: 0xf0006000 + 0x10 = 0xf0006010
LIME_TOP_FPGACFG_MAJOR_REV
Address: 0xf0006000 + 0x14 = 0xf0006014
LIME_TOP_FPGACFG_COMPILE_REV
Address: 0xf0006000 + 0x18 = 0xf0006018
LIME_TOP_FPGACFG_RESERVED_03
Address: 0xf0006000 + 0x1c = 0xf000601c
LIME_TOP_FPGACFG_RESERVED_04
Address: 0xf0006000 + 0x20 = 0xf0006020
LIME_TOP_FPGACFG_RESERVED_05
Address: 0xf0006000 + 0x24 = 0xf0006024
LIME_TOP_FPGACFG_RESERVED_06
Address: 0xf0006000 + 0x28 = 0xf0006028
LIME_TOP_FPGACFG_CH_EN
Address: 0xf0006000 + 0x2c = 0xf000602c
4b0001 - Channel A, 4b0010 - Channel B enabled, 4b0100 - Channel C enabled, 4b1000 - Channel D enabled,2b1111 - Channels A, B, C, D Enabled
LIME_TOP_FPGACFG_REG08
Address: 0xf0006000 + 0x30 = 0xf0006030
Field |
Name |
Description |
|---|---|---|
LIME_TOP_FPGACFG_REG09
Address: 0xf0006000 + 0x34 = 0xf0006034
Field |
Name |
Description |
|---|---|---|
LIME_TOP_FPGACFG_REG10
Address: 0xf0006000 + 0x38 = 0xf0006038
Field |
Name |
Description |
|---|---|---|
LIME_TOP_FPGACFG_WFM_CH_EN
Address: 0xf0006000 + 0x3c = 0xf000603c
LIME_TOP_FPGACFG_REG13
Address: 0xf0006000 + 0x40 = 0xf0006040
Field |
Name |
Description |
|---|---|---|
LIME_TOP_FPGACFG_WFM_SMPL_WIDTH
Address: 0xf0006000 + 0x44 = 0xf0006044
LIME_TOP_FPGACFG_SYNC_SIZE
Address: 0xf0006000 + 0x48 = 0xf0006048
LIME_TOP_FPGACFG_TXANT_PRE
Address: 0xf0006000 + 0x4c = 0xf000604c
LIME_TOP_FPGACFG_TXANT_POST
Address: 0xf0006000 + 0x50 = 0xf0006050
LIME_TOP_FPGACFG_REG18
Address: 0xf0006000 + 0x54 = 0xf0006054
Field |
Name |
Description |
|---|---|---|
[1] |
TCXO_EN |
TCXO Enable: 0: Disabled, 1: Enabled. |
[2] |
EXT_CLK |
CLK source select: 0: Internal, 1: External. |
LIME_TOP_FPGACFG_CLK_ENA
Address: 0xf0006000 + 0x58 = 0xf0006058
LIME_TOP_FPGACFG_SYNC_PULSE_PERIOD
Address: 0xf0006000 + 0x5c = 0xf000605c
LIME_TOP_RXTX_TOP_DDR2_1_STATUS
Address: 0xf0006000 + 0x60 = 0xf0006060
LIME_TOP_RXTX_TOP_DDR2_1_PNF_PER_BIT_L
Address: 0xf0006000 + 0x64 = 0xf0006064
LIME_TOP_RXTX_TOP_DDR2_1_PNF_PER_BIT_H
Address: 0xf0006000 + 0x68 = 0xf0006068
LIME_TOP_RXTX_TOP_RX_PATH_PKT_SIZE
Address: 0xf0006000 + 0x6c = 0xf000606c
Packet Size in bytes,