PCIE_ENDPOINT

Register Listing for PCIE_ENDPOINT

Register	Address
PCIE_ENDPOINT_PHY_LINK_STATUS	0xf000a000
PCIE_ENDPOINT_PHY_MSI_ENABLE	0xf000a004
PCIE_ENDPOINT_PHY_MSIX_ENABLE	0xf000a008
PCIE_ENDPOINT_PHY_BUS_MASTER_ENABLE	0xf000a00c
PCIE_ENDPOINT_PHY_MAX_REQUEST_SIZE	0xf000a010
PCIE_ENDPOINT_PHY_MAX_PAYLOAD_SIZE	0xf000a014

PCIE_ENDPOINT_PHY_LINK_STATUS

Address: 0xf000a000 + 0x0 = 0xf000a000

Field	Name	Description
[0]	STATUS	Value Description 0b0 Link Down. 0b1 Link Up.
[1]	RATE	Value Description 0b0 2.5 Gb/s. 0b1 5.0 Gb/s.
[3:2]	WIDTH	Value Description 0b00 1-Lane link. 0b01 2-Lane link. 0b10 4-Lane link. 0b11 8-Lane link.
[9:4]	LTSSM	LTSSM State

PCIE_ENDPOINT_PHY_MSI_ENABLE

Address: 0xf000a000 + 0x4 = 0xf000a004

MSI Enable Status. 1: MSI is enabled.

PCIE_ENDPOINT_PHY_MSIX_ENABLE

Address: 0xf000a000 + 0x8 = 0xf000a008

MSI-X Enable Status. 1: MSI-X is enabled.

PCIE_ENDPOINT_PHY_BUS_MASTER_ENABLE

Address: 0xf000a000 + 0xc = 0xf000a00c

Bus Mastering Status. 1: Bus Mastering enabled.

PCIE_ENDPOINT_PHY_MAX_REQUEST_SIZE

Address: 0xf000a000 + 0x10 = 0xf000a010

Negiotiated Max Request Size (in bytes).

PCIE_ENDPOINT_PHY_MAX_PAYLOAD_SIZE

Address: 0xf000a000 + 0x14 = 0xf000a014

Negiotiated Max Payload Size (in bytes).