LIME_TOP

Register Listing for LIME_TOP

Register	Address
LIME_TOP_EV_STATUS	0xf0005000
LIME_TOP_EV_PENDING	0xf0005004
LIME_TOP_EV_ENABLE	0xf0005008
LIME_TOP_GPO	0xf000500c
LIME_TOP_FPGACFG_BOARD_ID	0xf0005010
LIME_TOP_FPGACFG_MAJOR_REV	0xf0005014
LIME_TOP_FPGACFG_COMPILE_REV	0xf0005018
LIME_TOP_FPGACFG_RESERVED_03	0xf000501c
LIME_TOP_FPGACFG_RESERVED_04	0xf0005020
LIME_TOP_FPGACFG_RESERVED_05	0xf0005024
LIME_TOP_FPGACFG_RESERVED_06	0xf0005028
LIME_TOP_FPGACFG_CH_EN	0xf000502c
LIME_TOP_FPGACFG_REG08	0xf0005030
LIME_TOP_FPGACFG_REG09	0xf0005034
LIME_TOP_FPGACFG_REG10	0xf0005038
LIME_TOP_FPGACFG_WFM_CH_EN	0xf000503c
LIME_TOP_FPGACFG_REG13	0xf0005040
LIME_TOP_FPGACFG_WFM_SMPL_WIDTH	0xf0005044
LIME_TOP_FPGACFG_SYNC_SIZE	0xf0005048
LIME_TOP_FPGACFG_TXANT_PRE	0xf000504c
LIME_TOP_FPGACFG_TXANT_POST	0xf0005050
LIME_TOP_FPGACFG_REG18	0xf0005054
LIME_TOP_FPGACFG_CLK_ENA	0xf0005058
LIME_TOP_FPGACFG_SYNC_PULSE_PERIOD	0xf000505c
LIME_TOP_LMS7002_TOP_LMS_CTR_GPIO	0xf0005060
LIME_TOP_LMS7002_TOP_LMS1	0xf0005064
LIME_TOP_LMS7002_TOP_REG01	0xf0005068
LIME_TOP_LMS7002_TOP_REG03	0xf000506c
LIME_TOP_LMS7002_TOP_CMP_START	0xf0005070
LIME_TOP_LMS7002_TOP_CMP_LENGTH	0xf0005074
LIME_TOP_LMS7002_TOP_CMP_DONE	0xf0005078
LIME_TOP_LMS7002_TOP_CMP_ERROR	0xf000507c
LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_DRCT_TXCLK_EN	0xf0005080
LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_DRCT_RXCLK_EN	0xf0005084
LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PHCFG_MODE	0xf0005088
LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PHCFG_DONE	0xf000508c
LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PHCFG_ERR	0xf0005090
LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PLLCFG_DONE	0xf0005094
LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PLLCFG_BUSY	0xf0005098
LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PLLCFG_START	0xf000509c
LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PLLRST_START	0xf00050a0
LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PLL_IND	0xf00050a4
LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PHCFG_START	0xf00050a8
LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PLLCFG_ERROR	0xf00050ac
LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_VCO_MULT_BYP	0xf00050b0
LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_VCO_DIV_BYP	0xf00050b4
LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_C0_DIV_BYP	0xf00050b8
LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_C1_DIV_BYP	0xf00050bc
LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_VCO_DIV_CNT	0xf00050c0
LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_VCO_MULT_CNT	0xf00050c4
LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_C0_DIV_CNT	0xf00050c8
LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_C1_DIV_CNT	0xf00050cc
LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_C1_PHASE	0xf00050d0
LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_AUTO_PHCFG_SMPLS	0xf00050d4
LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_CSR_RESET	0xf00050d8
LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_DRP_RESET	0xf00050dc
LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_DRP_LOCKED	0xf00050e0
LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_DRP_READ	0xf00050e4
LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_DRP_WRITE	0xf00050e8
LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_DRP_DRDY	0xf00050ec
LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_DRP_ADR	0xf00050f0
LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_DRP_DAT_W	0xf00050f4
LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_DRP_DAT_R	0xf00050f8
LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_LATCHED_DRDY	0xf00050fc
LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_LATCHED_DRDY_RESET	0xf0005100
LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_CSR_RESET	0xf0005104
LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_DRP_RESET	0xf0005108
LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_DRP_LOCKED	0xf000510c
LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_DRP_READ	0xf0005110
LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_DRP_WRITE	0xf0005114
LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_DRP_DRDY	0xf0005118
LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_DRP_ADR	0xf000511c
LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_DRP_DAT_W	0xf0005120
LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_DRP_DAT_R	0xf0005124
LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_LATCHED_DRDY	0xf0005128
LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_LATCHED_DRDY_RESET	0xf000512c
LIME_TOP_RXTX_TOP_DDR2_1_STATUS	0xf0005130
LIME_TOP_RXTX_TOP_DDR2_1_PNF_PER_BIT_L	0xf0005134
LIME_TOP_RXTX_TOP_DDR2_1_PNF_PER_BIT_H	0xf0005138
LIME_TOP_RXTX_TOP_RX_PATH_PKT_SIZE	0xf000513c
LIME_TOP_RXTX_TOP_RX_PATH_TIMESTAMP_SETTINGS	0xf0005140
LIME_TOP_RX_DELAY_MODE	0xf0005144
LIME_TOP_TX_DELAY_MODE	0xf0005148
LIME_TOP_RFSW_CONTROL_TDD_MANUAL_VAL	0xf000514c
LIME_TOP_RFSW_CONTROL_TDD_AUTO_EN	0xf0005150
LIME_TOP_RFSW_CONTROL_TDD_INVERT	0xf0005154
LIME_TOP_RFSW_CONTROL_RFSW_RX	0xf0005158
LIME_TOP_RFSW_CONTROL_RFSW_TX	0xf000515c
LIME_TOP_RFSW_CONTROL_RFSW_AUTO_EN	0xf0005160
LIME_TOP_RX_TIME_MIN_SEC	0xf0005164
LIME_TOP_RX_TIME_MON_DAY_HRS	0xf0005168
LIME_TOP_RX_TIME_YRS	0xf000516c
LIME_TOP_TX_TIME_MIN_SEC	0xf0005170
LIME_TOP_TX_TIME_MON_DAY_HRS	0xf0005174
LIME_TOP_TX_TIME_YRS	0xf0005178

LIME_TOP_EV_STATUS

Address: 0xf0005000 + 0x0 = 0xf0005000

This register contains the current raw level of the clk_ctrl_irq event trigger. Writes to this register have no effect.

Field	Name	Description
[0]	CLK_CTRL_IRQ	Level of the clk_ctrl_irq event

LIME_TOP_EV_PENDING

Address: 0xf0005000 + 0x4 = 0xf0005004

When a clk_ctrl_irq event occurs, the corresponding bit will be set in this register. To clear the Event, set the corresponding bit in this register.

Field	Name	Description
[0]	CLK_CTRL_IRQ	1 if a clk_ctrl_irq event occurred. This Event is triggered on falling edge.

LIME_TOP_EV_ENABLE

Address: 0xf0005000 + 0x8 = 0xf0005008

This register enables the corresponding clk_ctrl_irq events. Write a 0 to this register to disable individual events.

Field	Name	Description
[0]	CLK_CTRL_IRQ	Write a 1 to enable the clk_ctrl_irq Event

LIME_TOP_GPO

Address: 0xf0005000 + 0xc = 0xf000500c

GPO interface

Field	Name	Description
[0]	CPU_BUSY	CPU state. Value Description 0b0 IDLE. 0b1 BUSY.

LIME_TOP_FPGACFG_BOARD_ID

Address: 0xf0005000 + 0x10 = 0xf0005010

LIME_TOP_FPGACFG_MAJOR_REV

Address: 0xf0005000 + 0x14 = 0xf0005014

LIME_TOP_FPGACFG_COMPILE_REV

Address: 0xf0005000 + 0x18 = 0xf0005018

LIME_TOP_FPGACFG_RESERVED_03

Address: 0xf0005000 + 0x1c = 0xf000501c

LIME_TOP_FPGACFG_RESERVED_04

Address: 0xf0005000 + 0x20 = 0xf0005020

LIME_TOP_FPGACFG_RESERVED_05

Address: 0xf0005000 + 0x24 = 0xf0005024

LIME_TOP_FPGACFG_RESERVED_06

Address: 0xf0005000 + 0x28 = 0xf0005028

LIME_TOP_FPGACFG_CH_EN

Address: 0xf0005000 + 0x2c = 0xf000502c

2b01 - Channel A, 2b10 - Channel B enabled, 2b11 - Channels A and B

LIME_TOP_FPGACFG_REG08

Address: 0xf0005000 + 0x30 = 0xf0005030

Field	Name	Description

LIME_TOP_FPGACFG_REG09

Address: 0xf0005000 + 0x34 = 0xf0005034

Field	Name	Description

LIME_TOP_FPGACFG_REG10

Address: 0xf0005000 + 0x38 = 0xf0005038

Field	Name	Description

LIME_TOP_FPGACFG_WFM_CH_EN

Address: 0xf0005000 + 0x3c = 0xf000503c

LIME_TOP_FPGACFG_REG13

Address: 0xf0005000 + 0x40 = 0xf0005040

Field	Name	Description

LIME_TOP_FPGACFG_WFM_SMPL_WIDTH

Address: 0xf0005000 + 0x44 = 0xf0005044

LIME_TOP_FPGACFG_SYNC_SIZE

Address: 0xf0005000 + 0x48 = 0xf0005048

LIME_TOP_FPGACFG_TXANT_PRE

Address: 0xf0005000 + 0x4c = 0xf000504c

LIME_TOP_FPGACFG_TXANT_POST

Address: 0xf0005000 + 0x50 = 0xf0005050

LIME_TOP_FPGACFG_REG18

Address: 0xf0005000 + 0x54 = 0xf0005054

Field	Name	Description
[1]	TCXO_EN	TCXO Enable: 0: Disabled, 1: Enabled.
[2]	EXT_CLK	CLK source select: 0: Internal, 1: External.

LIME_TOP_FPGACFG_CLK_ENA

Address: 0xf0005000 + 0x58 = 0xf0005058

LIME_TOP_FPGACFG_SYNC_PULSE_PERIOD

Address: 0xf0005000 + 0x5c = 0xf000505c

LIME_TOP_LMS7002_TOP_LMS_CTR_GPIO

Address: 0xf0005000 + 0x60 = 0xf0005060

LMS Control GPIOs.

LIME_TOP_LMS7002_TOP_LMS1

Address: 0xf0005000 + 0x64 = 0xf0005064

Field	Name	Description

LIME_TOP_LMS7002_TOP_REG01

Address: 0xf0005000 + 0x68 = 0xf0005068

LIME_TOP_LMS7002_TOP_REG03

Address: 0xf0005000 + 0x6c = 0xf000506c

Field	Name	Description

LIME_TOP_LMS7002_TOP_CMP_START

Address: 0xf0005000 + 0x70 = 0xf0005070

Start sample compare: 0: idle, 1 transition: start configuration

LIME_TOP_LMS7002_TOP_CMP_LENGTH

Address: 0xf0005000 + 0x74 = 0xf0005074

Sample compare length

LIME_TOP_LMS7002_TOP_CMP_DONE

Address: 0xf0005000 + 0x78 = 0xf0005078

Sample compare done: 0: Not done, 1: Done

LIME_TOP_LMS7002_TOP_CMP_ERROR

Address: 0xf0005000 + 0x7c = 0xf000507c

Sample compare error: 0: No error, 1: Error

LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_DRCT_TXCLK_EN

Address: 0xf0005000 + 0x80 = 0xf0005080

TX CLK source selection: 0: PLL, 1: Direct clock

LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_DRCT_RXCLK_EN

Address: 0xf0005000 + 0x84 = 0xf0005084

RX CLK source selection: 0: PLL, 1: Direct clock

LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PHCFG_MODE

Address: 0xf0005000 + 0x88 = 0xf0005088

Phase configuration mode: 0: Manual, 1: Auto

LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PHCFG_DONE

Address: 0xf0005000 + 0x8c = 0xf000508c

Phase config done: 0: Not done, 1: Done

LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PHCFG_ERR

Address: 0xf0005000 + 0x90 = 0xf0005090

Phase config error: 0: no error, 1: error

LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PLLCFG_DONE

Address: 0xf0005000 + 0x94 = 0xf0005094

PLL configuration done: 0: Not done, 1: Done

LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PLLCFG_BUSY

Address: 0xf0005000 + 0x98 = 0xf0005098

Clock config busy: 0: Idle, 1: Busy

LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PLLCFG_START

Address: 0xf0005000 + 0x9c = 0xf000509c

Start PLL configuration: 0: idle, 0 to 1 transition: start configuration

LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PLLRST_START

Address: 0xf0005000 + 0xa0 = 0xf00050a0

Start PLL reset: 0: idle, 0 to 1 transition: start configuration

LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PLL_IND

Address: 0xf0005000 + 0xa4 = 0xf00050a4

PLL/MMCM index for reconfiguration: 0: TX PLL, 1: RX PLL

LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PHCFG_START

Address: 0xf0005000 + 0xa8 = 0xf00050a8

Start phase configuration: 0: idle, 0 to 1 transition: start configuration

LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PLLCFG_ERROR

Address: 0xf0005000 + 0xac = 0xf00050ac

PLL configuration error: 0: no error, 1: error

LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_VCO_MULT_BYP

Address: 0xf0005000 + 0xb0 = 0xf00050b0

PLL multiplier bypass: 0: do not bypass, 1: bypass

LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_VCO_DIV_BYP

Address: 0xf0005000 + 0xb4 = 0xf00050b4

PLL divider bypass: 0: do not bypass, 1: bypass

LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_C0_DIV_BYP

Address: 0xf0005000 + 0xb8 = 0xf00050b8

Clock output 0 divider bypass: 0: do not bypass, 1: bypass

LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_C1_DIV_BYP

Address: 0xf0005000 + 0xbc = 0xf00050bc

Clock output 1 divider bypass: 0: do not bypass, 1: bypass

LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_VCO_DIV_CNT

Address: 0xf0005000 + 0xc0 = 0xf00050c0

PLL VCO divider counter values

LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_VCO_MULT_CNT

Address: 0xf0005000 + 0xc4 = 0xf00050c4

PLL VCO multiplier counter values

LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_C0_DIV_CNT

Address: 0xf0005000 + 0xc8 = 0xf00050c8

Clock output 0 divider counter values

LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_C1_DIV_CNT

Address: 0xf0005000 + 0xcc = 0xf00050cc

Clock output 1 divider counter values

LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_C1_PHASE

Address: 0xf0005000 + 0xd0 = 0xf00050d0

Clock output 1 phase offset, in degrees

LIME_TOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_AUTO_PHCFG_SMPLS

Address: 0xf0005000 + 0xd4 = 0xf00050d4

Number of samples to use during auto phase configuration

LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_CSR_RESET

Address: 0xf0005000 + 0xd8 = 0xf00050d8

LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_DRP_RESET

Address: 0xf0005000 + 0xdc = 0xf00050dc

LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_DRP_LOCKED

Address: 0xf0005000 + 0xe0 = 0xf00050e0

LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_DRP_READ

Address: 0xf0005000 + 0xe4 = 0xf00050e4

LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_DRP_WRITE

Address: 0xf0005000 + 0xe8 = 0xf00050e8

LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_DRP_DRDY

Address: 0xf0005000 + 0xec = 0xf00050ec

LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_DRP_ADR

Address: 0xf0005000 + 0xf0 = 0xf00050f0

LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_DRP_DAT_W

Address: 0xf0005000 + 0xf4 = 0xf00050f4

LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_DRP_DAT_R

Address: 0xf0005000 + 0xf8 = 0xf00050f8

LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_LATCHED_DRDY

Address: 0xf0005000 + 0xfc = 0xf00050fc

LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_LATCHED_DRDY_RESET

Address: 0xf0005000 + 0x100 = 0xf0005100

LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_CSR_RESET

Address: 0xf0005000 + 0x104 = 0xf0005104

LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_DRP_RESET

Address: 0xf0005000 + 0x108 = 0xf0005108

LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_DRP_LOCKED

Address: 0xf0005000 + 0x10c = 0xf000510c

LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_DRP_READ

Address: 0xf0005000 + 0x110 = 0xf0005110

LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_DRP_WRITE

Address: 0xf0005000 + 0x114 = 0xf0005114

LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_DRP_DRDY

Address: 0xf0005000 + 0x118 = 0xf0005118

LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_DRP_ADR

Address: 0xf0005000 + 0x11c = 0xf000511c

LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_DRP_DAT_W

Address: 0xf0005000 + 0x120 = 0xf0005120

LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_DRP_DAT_R

Address: 0xf0005000 + 0x124 = 0xf0005124

LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_LATCHED_DRDY

Address: 0xf0005000 + 0x128 = 0xf0005128

LIME_TOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_LATCHED_DRDY_RESET

Address: 0xf0005000 + 0x12c = 0xf000512c

LIME_TOP_RXTX_TOP_DDR2_1_STATUS

Address: 0xf0005000 + 0x130 = 0xf0005130

LIME_TOP_RXTX_TOP_DDR2_1_PNF_PER_BIT_L

Address: 0xf0005000 + 0x134 = 0xf0005134

LIME_TOP_RXTX_TOP_DDR2_1_PNF_PER_BIT_H

Address: 0xf0005000 + 0x138 = 0xf0005138

LIME_TOP_RXTX_TOP_RX_PATH_PKT_SIZE

Address: 0xf0005000 + 0x13c = 0xf000513c

Packet Size in bytes,

LIME_TOP_RXTX_TOP_RX_PATH_TIMESTAMP_SETTINGS

Address: 0xf0005000 + 0x140 = 0xf0005140

Timestamp Settings

Field	Name	Description
[0]	TS_SEL	Timestamp selector Value Description 0b0 Classic Timestamp. 0b1 PPS Counter+Clock counter mixed Timestamp.

LIME_TOP_RX_DELAY_MODE

Address: 0xf0005000 + 0x144 = 0xf0005144

RX enable signal delay mode

Field	Name	Description
[1:0]	RX_DEL_SEL	RX enable signal delay mode Value Description 0b0 No Delay. 0b1 Delay until PPS 0b2 Delay until PPS and Valid

LIME_TOP_TX_DELAY_MODE

Address: 0xf0005000 + 0x148 = 0xf0005148

TX enable signal delay mode

Field	Name	Description
[1:0]	TX_DEL_SEL	TX enable signal delay mode Value Description 0b0 No Delay. 0b1 Delay until PPS 0b2 Delay until PPS and Valid

LIME_TOP_RFSW_CONTROL_TDD_MANUAL_VAL

Address: 0xf0005000 + 0x14c = 0xf000514c

TDD Signal manual control value

LIME_TOP_RFSW_CONTROL_TDD_AUTO_EN

Address: 0xf0005000 + 0x150 = 0xf0005150

0- TDD auto control disabled, 1-TDD auto control enabled

LIME_TOP_RFSW_CONTROL_TDD_INVERT

Address: 0xf0005000 + 0x154 = 0xf0005154

0- TDD Control signal not inverted, 1- TDD Control signal inverted

LIME_TOP_RFSW_CONTROL_RFSW_RX

Address: 0xf0005000 + 0x158 = 0xf0005158

00- RF1 (WIDE), 01- RF2 (LOW), 10- RF3 (HIGH)

LIME_TOP_RFSW_CONTROL_RFSW_TX

Address: 0xf0005000 + 0x15c = 0xf000515c

0- TX1_2 (BAND2), 1- TX1_1 (BAND1)

LIME_TOP_RFSW_CONTROL_RFSW_AUTO_EN

Address: 0xf0005000 + 0x160 = 0xf0005160

0- RFSW Auto control disabled, 1- RFSW Auto control Enabled

LIME_TOP_RX_TIME_MIN_SEC

Address: 0xf0005000 + 0x164 = 0xf0005164

Time in minutes and seconds, when RX stream started

Field	Name	Description
[5:0]	SEC	RX stream start time, seconds
[11:6]	MIN	RX stream start time, minutes

LIME_TOP_RX_TIME_MON_DAY_HRS

Address: 0xf0005000 + 0x168 = 0xf0005168

Time in months, days and hours, when RX stream started

Field	Name	Description
[4:0]	HRS	RX stream start time, hours
[9:5]	DAY	RX stream start time, days
[13:10]	MON	RX stream start time, months

LIME_TOP_RX_TIME_YRS

Address: 0xf0005000 + 0x16c = 0xf000516c

Time in years, when RX stream started

Field	Name	Description
[11:0]	YRS	RX stream start time, years

LIME_TOP_TX_TIME_MIN_SEC

Address: 0xf0005000 + 0x170 = 0xf0005170

Time in minutes and seconds, when TX stream started

Field	Name	Description
[5:0]	SEC	TX stream start time, seconds
[11:6]	MIN	TX stream start time, minutes

LIME_TOP_TX_TIME_MON_DAY_HRS

Address: 0xf0005000 + 0x174 = 0xf0005174

Time in months, days and hours, when TX stream started

Field	Name	Description
[4:0]	HRS	TX stream start time, hours
[9:5]	DAY	TX stream start time, days
[13:10]	MON	TX stream start time, months

LIME_TOP_TX_TIME_YRS

Address: 0xf0005000 + 0x178 = 0xf0005178

Time in years, when TX stream started

Field	Name	Description
[11:0]	YRS	TX stream start time, years