GPIO_CONTROL
Register Listing for GPIO_CONTROL
Register |
Address |
|---|---|
GPIO_CONTROL_PORT_DIRECTION_U114 |
0xf0004000 |
GPIO_CONTROL_PORT_DIRECTION_U113 |
0xf0004004 |
GPIO_CONTROL_PORT_DIRECTION_U115 |
0xf0004008 |
GPIO_CONTROL_PORT_DIRECTION_U110 |
0xf000400c |
GPIO_CONTROL_POLARITY_INVERSION_U114 |
0xf0004010 |
GPIO_CONTROL_POLARITY_INVERSION_U113 |
0xf0004014 |
GPIO_CONTROL_POLARITY_INVERSION_U115 |
0xf0004018 |
GPIO_CONTROL_POLARITY_INVERSION_U110 |
0xf000401c |
GPIO_CONTROL_PORT_OUT_VALUE_114 |
0xf0004020 |
GPIO_CONTROL_PORT_OUT_VALUE_113 |
0xf0004024 |
GPIO_CONTROL_PORT_OUT_VALUE_115 |
0xf0004028 |
GPIO_CONTROL_PORT_OUT_VALUE_110 |
0xf000402c |
GPIO_CONTROL_PORT_IN_VALUE_114 |
0xf0004030 |
GPIO_CONTROL_PORT_IN_VALUE_113 |
0xf0004034 |
GPIO_CONTROL_PORT_IN_VALUE_115 |
0xf0004038 |
GPIO_CONTROL_PORT_IN_VALUE_110 |
0xf000403c |
GPIO_CONTROL_GPIO |
0xf0004040 |
GPIO_CONTROL_GPIO2 |
0xf0004044 |
GPIO_CONTROL_TDD_TXANT_PRE |
0xf0004048 |
GPIO_CONTROL_TDD_TXANT_POST |
0xf000404c |
GPIO_CONTROL_TDDCONTROLENABLE |
0xf0004050 |
GPIO_CONTROL_TDDSIGNALINVERT |
0xf0004054 |
GPIO_CONTROL_REGISTER_CONTROL |
0xf0004058 |
GPIO_CONTROL_PORT_DIRECTION_U114
Address: 0xf0004000 + 0x0 = 0xf0004000
GPIO direction: 1: Input, 0: Output
GPIO_CONTROL_PORT_DIRECTION_U113
Address: 0xf0004000 + 0x4 = 0xf0004004
GPIO direction: 1: Input, 0: Output
GPIO_CONTROL_PORT_DIRECTION_U115
Address: 0xf0004000 + 0x8 = 0xf0004008
GPIO direction: 1: Input, 0: Output
GPIO_CONTROL_PORT_DIRECTION_U110
Address: 0xf0004000 + 0xc = 0xf000400c
GPIO direction: 1: Input, 0: Output
GPIO_CONTROL_POLARITY_INVERSION_U114
Address: 0xf0004000 + 0x10 = 0xf0004010
GPIO polarity: 1: Inverted, 0: Normal
GPIO_CONTROL_POLARITY_INVERSION_U113
Address: 0xf0004000 + 0x14 = 0xf0004014
GPIO polarity: 1: Inverted, 0: Normal
GPIO_CONTROL_POLARITY_INVERSION_U115
Address: 0xf0004000 + 0x18 = 0xf0004018
GPIO polarity: 1: Inverted, 0: Normal
GPIO_CONTROL_POLARITY_INVERSION_U110
Address: 0xf0004000 + 0x1c = 0xf000401c
GPIO polarity: 1: Inverted, 0: Normal
GPIO_CONTROL_PORT_OUT_VALUE_114
Address: 0xf0004000 + 0x20 = 0xf0004020
GPIO output value: 1: High, 0: Low
GPIO_CONTROL_PORT_OUT_VALUE_113
Address: 0xf0004000 + 0x24 = 0xf0004024
GPIO output value: 1: High, 0: Low
GPIO_CONTROL_PORT_OUT_VALUE_115
Address: 0xf0004000 + 0x28 = 0xf0004028
GPIO output value: 1: High, 0: Low
GPIO_CONTROL_PORT_OUT_VALUE_110
Address: 0xf0004000 + 0x2c = 0xf000402c
GPIO output value: 1: High, 0: Low
GPIO_CONTROL_PORT_IN_VALUE_114
Address: 0xf0004000 + 0x30 = 0xf0004030
GPIO input value: 1: High, 0: Low
GPIO_CONTROL_PORT_IN_VALUE_113
Address: 0xf0004000 + 0x34 = 0xf0004034
GPIO input value: 1: High, 0: Low
GPIO_CONTROL_PORT_IN_VALUE_115
Address: 0xf0004000 + 0x38 = 0xf0004038
GPIO input value: 1: High, 0: Low
GPIO_CONTROL_PORT_IN_VALUE_110
Address: 0xf0004000 + 0x3c = 0xf000403c
GPIO input value: 1: High, 0: Low
GPIO_CONTROL_GPIO
Address: 0xf0004000 + 0x40 = 0xf0004040
GPIO output value: 1: High, 0: Low
GPIO_CONTROL_GPIO2
Address: 0xf0004000 + 0x44 = 0xf0004044
GPIO output value: 1: High, 0: Low
GPIO_CONTROL_TDD_TXANT_PRE
Address: 0xf0004000 + 0x48 = 0xf0004048
Number of cycles to delay enabling TDD signal
GPIO_CONTROL_TDD_TXANT_POST
Address: 0xf0004000 + 0x4c = 0xf000404c
Number of cycles to delay disabling TDD signal
GPIO_CONTROL_TDDCONTROLENABLE
Address: 0xf0004000 + 0x50 = 0xf0004050
TDD Control Enable, bit per channel
GPIO_CONTROL_TDDSIGNALINVERT
Address: 0xf0004000 + 0x54 = 0xf0004054
TDD Signal Invert, bit per channel
GPIO_CONTROL_REGISTER_CONTROL
Address: 0xf0004000 + 0x58 = 0xf0004058
register control bitfield
Field |
Name |
Description |
|---|---|---|