LIMETOP

Register Listing for LIMETOP

Register	Address
LIMETOP_EV_STATUS	0xf0004800
LIMETOP_EV_PENDING	0xf0004804
LIMETOP_EV_ENABLE	0xf0004808
LIMETOP_GPO	0xf000480c
LIMETOP_FPGACFG_BOARD_ID	0xf0004810
LIMETOP_FPGACFG_MAJOR_REV	0xf0004814
LIMETOP_FPGACFG_COMPILE_REV	0xf0004818
LIMETOP_FPGACFG_RESERVED_03	0xf000481c
LIMETOP_FPGACFG_RESERVED_04	0xf0004820
LIMETOP_FPGACFG_RESERVED_05	0xf0004824
LIMETOP_FPGACFG_RESERVED_06	0xf0004828
LIMETOP_FPGACFG_CH_EN	0xf000482c
LIMETOP_FPGACFG_REG08	0xf0004830
LIMETOP_FPGACFG_REG09	0xf0004834
LIMETOP_FPGACFG_REG10	0xf0004838
LIMETOP_FPGACFG_WFM_CH_EN	0xf000483c
LIMETOP_FPGACFG_REG13	0xf0004840
LIMETOP_FPGACFG_WFM_SMPL_WIDTH	0xf0004844
LIMETOP_FPGACFG_SYNC_SIZE	0xf0004848
LIMETOP_FPGACFG_TXANT_PRE	0xf000484c
LIMETOP_FPGACFG_TXANT_POST	0xf0004850
LIMETOP_FPGACFG_REG18	0xf0004854
LIMETOP_FPGACFG_CLK_ENA	0xf0004858
LIMETOP_FPGACFG_SYNC_PULSE_PERIOD	0xf000485c
LIMETOP_LMS7002_TOP_LMS_CTR_GPIO	0xf0004860
LIMETOP_LMS7002_TOP_LMS1	0xf0004864
LIMETOP_LMS7002_TOP_REG01	0xf0004868
LIMETOP_LMS7002_TOP_REG03	0xf000486c
LIMETOP_LMS7002_TOP_CMP_START	0xf0004870
LIMETOP_LMS7002_TOP_CMP_LENGTH	0xf0004874
LIMETOP_LMS7002_TOP_CMP_DONE	0xf0004878
LIMETOP_LMS7002_TOP_CMP_ERROR	0xf000487c
LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_DRCT_TXCLK_EN	0xf0004880
LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_DRCT_RXCLK_EN	0xf0004884
LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PHCFG_MODE	0xf0004888
LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PHCFG_DONE	0xf000488c
LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PHCFG_ERR	0xf0004890
LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PLLCFG_DONE	0xf0004894
LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PLLCFG_BUSY	0xf0004898
LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PLLCFG_START	0xf000489c
LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PLLRST_START	0xf00048a0
LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PLL_IND	0xf00048a4
LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PHCFG_START	0xf00048a8
LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PLLCFG_ERROR	0xf00048ac
LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_VCO_MULT_BYP	0xf00048b0
LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_VCO_DIV_BYP	0xf00048b4
LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_C0_DIV_BYP	0xf00048b8
LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_C1_DIV_BYP	0xf00048bc
LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_VCO_DIV_CNT	0xf00048c0
LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_VCO_MULT_CNT	0xf00048c4
LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_C0_DIV_CNT	0xf00048c8
LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_C1_DIV_CNT	0xf00048cc
LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_C1_PHASE	0xf00048d0
LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_AUTO_PHCFG_SMPLS	0xf00048d4
LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_CSR_RESET	0xf00048d8
LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_DRP_RESET	0xf00048dc
LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_DRP_LOCKED	0xf00048e0
LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_DRP_READ	0xf00048e4
LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_DRP_WRITE	0xf00048e8
LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_DRP_DRDY	0xf00048ec
LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_DRP_ADR	0xf00048f0
LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_DRP_DAT_W	0xf00048f4
LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_DRP_DAT_R	0xf00048f8
LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_LATCHED_DRDY	0xf00048fc
LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_LATCHED_DRDY_RESET	0xf0004900
LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_CSR_RESET	0xf0004904
LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_DRP_RESET	0xf0004908
LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_DRP_LOCKED	0xf000490c
LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_DRP_READ	0xf0004910
LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_DRP_WRITE	0xf0004914
LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_DRP_DRDY	0xf0004918
LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_DRP_ADR	0xf000491c
LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_DRP_DAT_W	0xf0004920
LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_DRP_DAT_R	0xf0004924
LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_LATCHED_DRDY	0xf0004928
LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_LATCHED_DRDY_RESET	0xf000492c
LIMETOP_RXTX_TOP_DDR2_1_STATUS	0xf0004930
LIMETOP_RXTX_TOP_DDR2_1_PNF_PER_BIT_L	0xf0004934
LIMETOP_RXTX_TOP_DDR2_1_PNF_PER_BIT_H	0xf0004938
LIMETOP_RXTX_TOP_RX_PATH_PKT_SIZE	0xf000493c
LIMETOP_RXTX_TOP_RX_PATH_TIMESTAMP_SETTINGS	0xf0004940
LIMETOP_RX_DELAY_MODE	0xf0004944
LIMETOP_TX_DELAY_MODE	0xf0004948
LIMETOP_RFSW_CONTROL_TDD_MANUAL_VAL	0xf000494c
LIMETOP_RFSW_CONTROL_TDD_AUTO_EN	0xf0004950
LIMETOP_RFSW_CONTROL_TDD_INVERT	0xf0004954
LIMETOP_RFSW_CONTROL_RFSW_RX	0xf0004958
LIMETOP_RFSW_CONTROL_RFSW_TX	0xf000495c
LIMETOP_RFSW_CONTROL_RFSW_AUTO_EN	0xf0004960
LIMETOP_RX_TIME_MIN_SEC	0xf0004964
LIMETOP_RX_TIME_MON_DAY_HRS	0xf0004968
LIMETOP_RX_TIME_YRS	0xf000496c
LIMETOP_TX_TIME_MIN_SEC	0xf0004970
LIMETOP_TX_TIME_MON_DAY_HRS	0xf0004974
LIMETOP_TX_TIME_YRS	0xf0004978

LIMETOP_EV_STATUS

Address: 0xf0004800 + 0x0 = 0xf0004800

This register contains the current raw level of the clk_ctrl_irq event trigger. Writes to this register have no effect.

Field	Name	Description
[0]	CLK_CTRL_IRQ	Level of the clk_ctrl_irq event

LIMETOP_EV_PENDING

Address: 0xf0004800 + 0x4 = 0xf0004804

When a clk_ctrl_irq event occurs, the corresponding bit will be set in this register. To clear the Event, set the corresponding bit in this register.

Field	Name	Description
[0]	CLK_CTRL_IRQ	1 if a clk_ctrl_irq event occurred. This Event is triggered on falling edge.

LIMETOP_EV_ENABLE

Address: 0xf0004800 + 0x8 = 0xf0004808

This register enables the corresponding clk_ctrl_irq events. Write a 0 to this register to disable individual events.

Field	Name	Description
[0]	CLK_CTRL_IRQ	Write a 1 to enable the clk_ctrl_irq Event

LIMETOP_GPO

Address: 0xf0004800 + 0xc = 0xf000480c

GPO interface

Field	Name	Description
[0]	CPU_BUSY	CPU state. Value Description 0b0 IDLE. 0b1 BUSY.

LIMETOP_FPGACFG_BOARD_ID

Address: 0xf0004800 + 0x10 = 0xf0004810

LIMETOP_FPGACFG_MAJOR_REV

Address: 0xf0004800 + 0x14 = 0xf0004814

LIMETOP_FPGACFG_COMPILE_REV

Address: 0xf0004800 + 0x18 = 0xf0004818

LIMETOP_FPGACFG_RESERVED_03

Address: 0xf0004800 + 0x1c = 0xf000481c

LIMETOP_FPGACFG_RESERVED_04

Address: 0xf0004800 + 0x20 = 0xf0004820

LIMETOP_FPGACFG_RESERVED_05

Address: 0xf0004800 + 0x24 = 0xf0004824

LIMETOP_FPGACFG_RESERVED_06

Address: 0xf0004800 + 0x28 = 0xf0004828

LIMETOP_FPGACFG_CH_EN

Address: 0xf0004800 + 0x2c = 0xf000482c

4b0001 - Channel A, 4b0010 - Channel B enabled, 4b0100 - Channel C enabled, 4b1000 - Channel D enabled,2b1111 - Channels A, B, C, D Enabled

LIMETOP_FPGACFG_REG08

Address: 0xf0004800 + 0x30 = 0xf0004830

Field	Name	Description

LIMETOP_FPGACFG_REG09

Address: 0xf0004800 + 0x34 = 0xf0004834

Field	Name	Description

LIMETOP_FPGACFG_REG10

Address: 0xf0004800 + 0x38 = 0xf0004838

Field	Name	Description

LIMETOP_FPGACFG_WFM_CH_EN

Address: 0xf0004800 + 0x3c = 0xf000483c

LIMETOP_FPGACFG_REG13

Address: 0xf0004800 + 0x40 = 0xf0004840

Field	Name	Description

LIMETOP_FPGACFG_WFM_SMPL_WIDTH

Address: 0xf0004800 + 0x44 = 0xf0004844

LIMETOP_FPGACFG_SYNC_SIZE

Address: 0xf0004800 + 0x48 = 0xf0004848

LIMETOP_FPGACFG_TXANT_PRE

Address: 0xf0004800 + 0x4c = 0xf000484c

LIMETOP_FPGACFG_TXANT_POST

Address: 0xf0004800 + 0x50 = 0xf0004850

LIMETOP_FPGACFG_REG18

Address: 0xf0004800 + 0x54 = 0xf0004854

Field	Name	Description
[1]	TCXO_EN	TCXO Enable: 0: Disabled, 1: Enabled.
[2]	EXT_CLK	CLK source select: 0: Internal, 1: External.

LIMETOP_FPGACFG_CLK_ENA

Address: 0xf0004800 + 0x58 = 0xf0004858

LIMETOP_FPGACFG_SYNC_PULSE_PERIOD

Address: 0xf0004800 + 0x5c = 0xf000485c

LIMETOP_LMS7002_TOP_LMS_CTR_GPIO

Address: 0xf0004800 + 0x60 = 0xf0004860

LMS Control GPIOs.

LIMETOP_LMS7002_TOP_LMS1

Address: 0xf0004800 + 0x64 = 0xf0004864

Field	Name	Description

LIMETOP_LMS7002_TOP_REG01

Address: 0xf0004800 + 0x68 = 0xf0004868

LIMETOP_LMS7002_TOP_REG03

Address: 0xf0004800 + 0x6c = 0xf000486c

Field	Name	Description

LIMETOP_LMS7002_TOP_CMP_START

Address: 0xf0004800 + 0x70 = 0xf0004870

Start sample compare: 0: idle, 1 transition: start configuration

LIMETOP_LMS7002_TOP_CMP_LENGTH

Address: 0xf0004800 + 0x74 = 0xf0004874

Sample compare length

LIMETOP_LMS7002_TOP_CMP_DONE

Address: 0xf0004800 + 0x78 = 0xf0004878

Sample compare done: 0: Not done, 1: Done

LIMETOP_LMS7002_TOP_CMP_ERROR

Address: 0xf0004800 + 0x7c = 0xf000487c

Sample compare error: 0: No error, 1: Error

LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_DRCT_TXCLK_EN

Address: 0xf0004800 + 0x80 = 0xf0004880

TX CLK source selection: 0: PLL, 1: Direct clock

LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_DRCT_RXCLK_EN

Address: 0xf0004800 + 0x84 = 0xf0004884

RX CLK source selection: 0: PLL, 1: Direct clock

LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PHCFG_MODE

Address: 0xf0004800 + 0x88 = 0xf0004888

Phase configuration mode: 0: Manual, 1: Auto

LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PHCFG_DONE

Address: 0xf0004800 + 0x8c = 0xf000488c

Phase config done: 0: Not done, 1: Done

LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PHCFG_ERR

Address: 0xf0004800 + 0x90 = 0xf0004890

Phase config error: 0: no error, 1: error

LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PLLCFG_DONE

Address: 0xf0004800 + 0x94 = 0xf0004894

PLL configuration done: 0: Not done, 1: Done

LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PLLCFG_BUSY

Address: 0xf0004800 + 0x98 = 0xf0004898

Clock config busy: 0: Idle, 1: Busy

LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PLLCFG_START

Address: 0xf0004800 + 0x9c = 0xf000489c

Start PLL configuration: 0: idle, 0 to 1 transition: start configuration

LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PLLRST_START

Address: 0xf0004800 + 0xa0 = 0xf00048a0

Start PLL reset: 0: idle, 0 to 1 transition: start configuration

LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PLL_IND

Address: 0xf0004800 + 0xa4 = 0xf00048a4

PLL/MMCM index for reconfiguration: 0: TX PLL, 1: RX PLL

LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PHCFG_START

Address: 0xf0004800 + 0xa8 = 0xf00048a8

Start phase configuration: 0: idle, 0 to 1 transition: start configuration

LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_PLLCFG_ERROR

Address: 0xf0004800 + 0xac = 0xf00048ac

PLL configuration error: 0: no error, 1: error

LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_VCO_MULT_BYP

Address: 0xf0004800 + 0xb0 = 0xf00048b0

PLL multiplier bypass: 0: do not bypass, 1: bypass

LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_VCO_DIV_BYP

Address: 0xf0004800 + 0xb4 = 0xf00048b4

PLL divider bypass: 0: do not bypass, 1: bypass

LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_C0_DIV_BYP

Address: 0xf0004800 + 0xb8 = 0xf00048b8

Clock output 0 divider bypass: 0: do not bypass, 1: bypass

LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_C1_DIV_BYP

Address: 0xf0004800 + 0xbc = 0xf00048bc

Clock output 1 divider bypass: 0: do not bypass, 1: bypass

LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_VCO_DIV_CNT

Address: 0xf0004800 + 0xc0 = 0xf00048c0

PLL VCO divider counter values

LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_VCO_MULT_CNT

Address: 0xf0004800 + 0xc4 = 0xf00048c4

PLL VCO multiplier counter values

LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_C0_DIV_CNT

Address: 0xf0004800 + 0xc8 = 0xf00048c8

Clock output 0 divider counter values

LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_C1_DIV_CNT

Address: 0xf0004800 + 0xcc = 0xf00048cc

Clock output 1 divider counter values

LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_C1_PHASE

Address: 0xf0004800 + 0xd0 = 0xf00048d0

Clock output 1 phase offset, in degrees

LIMETOP_LMS7002_TOP_LMS7002_CLK_CLK_CTRL_AUTO_PHCFG_SMPLS

Address: 0xf0004800 + 0xd4 = 0xf00048d4

Number of samples to use during auto phase configuration

LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_CSR_RESET

Address: 0xf0004800 + 0xd8 = 0xf00048d8

LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_DRP_RESET

Address: 0xf0004800 + 0xdc = 0xf00048dc

LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_DRP_LOCKED

Address: 0xf0004800 + 0xe0 = 0xf00048e0

LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_DRP_READ

Address: 0xf0004800 + 0xe4 = 0xf00048e4

LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_DRP_WRITE

Address: 0xf0004800 + 0xe8 = 0xf00048e8

LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_DRP_DRDY

Address: 0xf0004800 + 0xec = 0xf00048ec

LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_DRP_ADR

Address: 0xf0004800 + 0xf0 = 0xf00048f0

LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_DRP_DAT_W

Address: 0xf0004800 + 0xf4 = 0xf00048f4

LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_DRP_DAT_R

Address: 0xf0004800 + 0xf8 = 0xf00048f8

LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_LATCHED_DRDY

Address: 0xf0004800 + 0xfc = 0xf00048fc

LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL0_TX_MMCM_LATCHED_DRDY_RESET

Address: 0xf0004800 + 0x100 = 0xf0004900

LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_CSR_RESET

Address: 0xf0004800 + 0x104 = 0xf0004904

LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_DRP_RESET

Address: 0xf0004800 + 0x108 = 0xf0004908

LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_DRP_LOCKED

Address: 0xf0004800 + 0x10c = 0xf000490c

LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_DRP_READ

Address: 0xf0004800 + 0x110 = 0xf0004910

LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_DRP_WRITE

Address: 0xf0004800 + 0x114 = 0xf0004914

LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_DRP_DRDY

Address: 0xf0004800 + 0x118 = 0xf0004918

LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_DRP_ADR

Address: 0xf0004800 + 0x11c = 0xf000491c

LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_DRP_DAT_W

Address: 0xf0004800 + 0x120 = 0xf0004920

LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_DRP_DAT_R

Address: 0xf0004800 + 0x124 = 0xf0004924

LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_LATCHED_DRDY

Address: 0xf0004800 + 0x128 = 0xf0004928

LIMETOP_LMS7002_TOP_LMS7002_CLK_PLL1_RX_MMCM_LATCHED_DRDY_RESET

Address: 0xf0004800 + 0x12c = 0xf000492c

LIMETOP_RXTX_TOP_DDR2_1_STATUS

Address: 0xf0004800 + 0x130 = 0xf0004930

LIMETOP_RXTX_TOP_DDR2_1_PNF_PER_BIT_L

Address: 0xf0004800 + 0x134 = 0xf0004934

LIMETOP_RXTX_TOP_DDR2_1_PNF_PER_BIT_H

Address: 0xf0004800 + 0x138 = 0xf0004938

LIMETOP_RXTX_TOP_RX_PATH_PKT_SIZE

Address: 0xf0004800 + 0x13c = 0xf000493c

Packet Size in bytes,

LIMETOP_RXTX_TOP_RX_PATH_TIMESTAMP_SETTINGS

Address: 0xf0004800 + 0x140 = 0xf0004940

Timestamp Settings

Field	Name	Description
[0]	TS_SEL	Timestamp selector Value Description 0b0 Classic Timestamp. 0b1 PPS Counter+Clock counter mixed Timestamp.

LIMETOP_RX_DELAY_MODE

Address: 0xf0004800 + 0x144 = 0xf0004944

RX enable signal delay mode

Field	Name	Description
[1:0]	RX_DEL_SEL	RX enable signal delay mode Value Description 0b0 No Delay. 0b1 Delay until PPS 0b2 Delay until PPS and Valid

LIMETOP_TX_DELAY_MODE

Address: 0xf0004800 + 0x148 = 0xf0004948

TX enable signal delay mode

Field	Name	Description
[1:0]	TX_DEL_SEL	TX enable signal delay mode Value Description 0b0 No Delay. 0b1 Delay until PPS 0b2 Delay until PPS and Valid

LIMETOP_RFSW_CONTROL_TDD_MANUAL_VAL

Address: 0xf0004800 + 0x14c = 0xf000494c

TDD Signal manual control value

LIMETOP_RFSW_CONTROL_TDD_AUTO_EN

Address: 0xf0004800 + 0x150 = 0xf0004950

0- TDD auto control disabled, 1-TDD auto control enabled

LIMETOP_RFSW_CONTROL_TDD_INVERT

Address: 0xf0004800 + 0x154 = 0xf0004954

0- TDD Control signal not inverted, 1- TDD Control signal inverted

LIMETOP_RFSW_CONTROL_RFSW_RX

Address: 0xf0004800 + 0x158 = 0xf0004958

00- RF1 (WIDE), 01- RF2 (LOW), 10- RF3 (HIGH)

LIMETOP_RFSW_CONTROL_RFSW_TX

Address: 0xf0004800 + 0x15c = 0xf000495c

0- TX1_2 (BAND2), 1- TX1_1 (BAND1)

LIMETOP_RFSW_CONTROL_RFSW_AUTO_EN

Address: 0xf0004800 + 0x160 = 0xf0004960

0- RFSW Auto control disabled, 1- RFSW Auto control Enabled

LIMETOP_RX_TIME_MIN_SEC

Address: 0xf0004800 + 0x164 = 0xf0004964

Time in minutes and seconds, when RX stream started

Field	Name	Description
[5:0]	SEC	RX stream start time, seconds
[11:6]	MIN	RX stream start time, minutes

LIMETOP_RX_TIME_MON_DAY_HRS

Address: 0xf0004800 + 0x168 = 0xf0004968

Time in months, days and hours, when RX stream started

Field	Name	Description
[4:0]	HRS	RX stream start time, hours
[9:5]	DAY	RX stream start time, days
[13:10]	MON	RX stream start time, months

LIMETOP_RX_TIME_YRS

Address: 0xf0004800 + 0x16c = 0xf000496c

Time in years, when RX stream started

Field	Name	Description
[11:0]	YRS	RX stream start time, years

LIMETOP_TX_TIME_MIN_SEC

Address: 0xf0004800 + 0x170 = 0xf0004970

Time in minutes and seconds, when TX stream started

Field	Name	Description
[5:0]	SEC	TX stream start time, seconds
[11:6]	MIN	TX stream start time, minutes

LIMETOP_TX_TIME_MON_DAY_HRS

Address: 0xf0004800 + 0x174 = 0xf0004974

Time in months, days and hours, when TX stream started

Field	Name	Description
[4:0]	HRS	TX stream start time, hours
[9:5]	DAY	TX stream start time, days
[13:10]	MON	TX stream start time, months

LIMETOP_TX_TIME_YRS

Address: 0xf0004800 + 0x178 = 0xf0004978

Time in years, when TX stream started

Field	Name	Description
[11:0]	YRS	TX stream start time, years