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LimeSDR FPGA Gateware
  • Introduction
  • Project Structure
    • Overview
    • LimeSDR_GW Repository Layout
    • LimeDFB Repository Layout
      • Integration Between Repos
    • Additional Files
  • Gateware Description
    • LimeSDR XTRX
      • Main Block Diagram
        • Soft core CPU Module
        • Lime_top Module
        • LMS7002 Top Module
        • RX Path Top Module
        • TX Path Top Module
        • PCIe PHY Module
        • I2C Modules
        • LMS SPI Module
      • Flash Module
      • Gateware Register Reference
        • Documentation for limesdr-xtrx
        • Modules
          • Interrupt Controller
        • Register Groups
          • UART
          • ICAP
          • PCIE_PHY
          • PCIE_MSI
          • AUX
          • PCIE_DMA0
          • CTRL
          • GPIO
          • IDENTIFIER_MEM
          • LEDS
          • LIME_TOP
          • LMS_CLOCK_TEST
          • MAIN
          • PCIE_UART0
          • PCIE_UART1
          • FLASH
          • XADC
          • DNA
          • I2C0
          • I2C1
          • PCIE_ENDPOINT
          • PERIPHCFG
          • PPSDO
          • SPIMASTER
          • SYS_CLOCK_TEST
          • TIMER0
          • CNTRL
          • VCTCXO_TAMER
        • Indices and tables
    • LimeSDR Mini V1
      • Main Block Diagram
      • Soft core CPU Module
      • Lime_top Module
        • LMS7002 Top Module
        • RX Path Top Module
        • TX Path Top Module
      • FT601 PHY Module
      • I2C Module
      • Lms_spi Module
      • Flash Module
    • LimeSDR Mini V2
      • Main Block Diagram
      • Soft core CPU Module
      • Lime_top Module
        • LMS7002 Top Module
        • RX Path Top Module
        • TX Path Top Module
      • FT601 PHY Module
      • I2C Module
      • Lms_spi Module
      • Flash Module
    • HiperSDR 44xx
      • Main Block Diagram
        • Soft core CPU Module
        • AFE79xx
        • LimeTop Module
        • RX Path Top Module
        • TX Path Top Module
        • PCIe PHY Module
        • I2C Modules
        • SPI Modules
        • Flash Module
      • HiperSDR_44xx RF controls
      • Gateware Register Reference
        • Documentation for hipersdr-44xx
        • Modules
          • Interrupt Controller
        • Register Groups
          • UART
          • PCIE_PHY
          • PCIE_MSI
          • AFE
          • PCIE_DMA0
          • CTRL
          • FPGACFG
          • GPIO_CONTROL
          • I2C3
          • IDENTIFIER_MEM
          • LEDS
          • LIME_TOP
          • FLASH
          • I2C0
          • I2C1
          • I2C2
          • SPIMASTER
          • SPIMASTER1
          • PCIE_ENDPOINT
          • PERIPHCFG
          • PWR_CONTROL
          • CNTRL
          • SPIMASTER_ADF
          • TIMER0
        • Indices and tables
    • Additional features
      • Compatibility table
        • UTC timestamping
          • Primary Code References
          • System Overview
          • PPS and UART Plumbing
          • UTC Extraction and Validity
          • RX Timestamps and Header Insertion
          • Software CSR Reference
          • Quick Setup Checklist
          • Edge Cases and Notes
          • Appendix: Header Decode Example
    • PCIe and USB Interfacing
      • Overview of Interface Options
      • USB Interface (FT601)
      • PCIe Interface (LitePCIe)
      • Testing and Debugging Interfaces
    • Toolchains
      • FPGA Synthesis Toolchains
      • RISC-V Firmware Toolchains
    • Gateware Update Mechanism
      • Overview
      • Update Process
      • Multiboot Across FPGAs
      • Testing and Recovery
  • Building the Project
    • Requirements
    • Cloning the Repository
    • Build/Load/Flash Instructions
      • LimeSDR XTRX
        • Available build options
        • User/Golden Bitstreams
        • Programming cables
        • Flashing Instructions
      • LimeSDR Mini V1
        • Available build options
        • User/Golden Bitstreams
        • Programming cables
        • Flashing Instructions
      • LimeSDR Mini V2
        • Available build options
        • User/Golden Bitstreams
        • Programming cables
        • Flashing Instructions
      • HiperSDR 44xx
        • Available build options
        • User/Golden Bitstreams
        • Programming cables
          • JTAG programming (openFPGALoader)
          • Used software and hardware
          • FT2232H Mini Module JTAG adapter
        • Flashing Instructions
  • LiteX Basics
    • Introduction to LiteX in LimeSDR_GW
      • Overview of LiteX usage in LimeSDR_GW
      • Benefits of Using LiteX (in the Context of LimeSDR_GW)
    • Understanding Core LiteX Concepts: Boards, Platforms, Targets
      • Platform = Board + Constraints
      • LMS7002M I/O Block on LimeSDR Mini V2
      • Timing Constraints Generation
      • Multiple Toolchain Support
      • Target = SoC Top-Level + Flow Control
      • How It All Fits Together
    • Creating LiteX/Migen Wrappers
      • Example: Wrapping the GPIO Module
      • General Pattern
  • Modifying the Project
    • Gateware
      • FFT module example
        • Instantiating FFT Example module
        • Connecting FFT Example module
        • Checking FFT results
    • Firmware
    • Firmware Loading via UART
    • Debug Tools
  • Adding a New Board
    • Tutorial: Developing New LimeDFB Blocks
    • Tutorial: Adding a Custom Board
  • Best Practices and Guidelines
    • Introduction
    • File, Module, and Signal Naming Conventions
      • Module and File Structure
      • Class Naming
      • Signal Naming
      • AXIStream Interfaces
      • CSRs and Registers
      • Platform Naming and IO Mapping
      • Recommendations
    • Developing for Portability Across Devices and Vendors
      • Unified Platform and IO Abstraction
      • Cross-Vendor IO Support: Abstracted Primitives
      • Cross-Vendor PLL and Clocking
      • Memory Abstraction and Flexibility
      • Simplified Toolchain Integration
      • Avoiding Fragmentation of CPU and Firmware
    • Soft CPU Core Options
      • Supported CPUs in LiteX
      • Tested Cores in LimeSDR_GW
      • Typical Firmware Workloads
      • Unified Firmware and Tooling
LimeSDR FPGA Gateware
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© Copyright 2024-2025, Lime Microsystems. Last updated on Feb 02, 2026.

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